Usage of non blocking assignments in verilog .....

[Muthuraja.M]

Hi friends ,

i know wat is non blocking assignments and how the delay get varied between blocking
and non blocking assignments..


But i need to know for which type of application we use blocking and for which type for
non blocking assignments..


pls explain


Thanks in advance...

- - - Updated - - -

reg reg1,reg2,clk,clk1;
initial
begin
clk=0;
clk1=0;
clk = #50 ~clk;
clk1 <= #50 ~clk1;
end

in this code clk is inverted after 50 units and clk1 is inverted after 100 units ...


reg reg1,reg2,clk,clk1;
initial
begin
clk=0;
clk1=0;
clk <= #50 ~clk;
clk1 = #50 ~clk1;
end


But for this code both are inverted at the same time 50 units .. why wat was happen.


pls explain...

 

[kranthi_vlsi]

Hi friends ,

i know wat is non blocking assignments and how the delay get varied between blocking
and non blocking assignments..


But i need to know for which type of application we use blocking and for which type for
non blocking assignments..


pls explain


Thanks in advance...

- - - Updated - - -

reg reg1,reg2,clk,clk1;
initial
begin
clk=0;
clk1=0;
clk = #50 ~clk;
clk1 <= #50 ~clk1;
end

in this code clk is inverted after 50 units and clk1 is inverted after 100 units ...


reg reg1,reg2,clk,clk1;
initial
begin
clk=0;
clk1=0;
clk <= #50 ~clk;
clk1 = #50 ~clk1;
end


But for this code both are inverted at the same time 50 units .. why wat was happen.


pls explain...

basic difference is blocking statements execute in sequential manner and non blocking statements execute in concurrent manner....in first code first 2 statements will execute in sequential manner with zero time delay after that nxt statement takes fifty time units delay den only execution goes to nxt statements it has intra delay and it takes another 50 units delay dats why clk1 is inverting after 100 units and clk is inverting after 50 units
in second code 3rd and 4 th ststements will execute in concurrent manner y because it 3 rd statement is non blocking

 

[FR1985]

hi can you tell what mean this instruction:
mem[wr_addr] <= i_data;
why we use mem and inside another reg
thank you

 

[kranthi_vlsi]

hi can you tell what mean this instruction:
mem[wr_addr] <= i_data;
why we use mem and inside another reg
thank you

here what ever the input data(i_data) u give is stored into the particular address (wr_addr) in the memory(mem)

 

[FR1985]

here what ever the input data(i_data) u give is stored into the particular address (wr_addr) in the memory(mem)

thank you very much for your explanation