[SOLVED] [Urgent]Frequency Compensation for Single Ended operational amplifier

[darkseid]

Dear All

I have designed an amplifier (circuit attached). I am getting a gain of 90 dB but the phase margin is 16 degrees.

Supply: 0 - 3V
Input Pair: Complementary MOS
Current Mirror: Self Biased Wide Swing Cascode Current mirror.



Any suggestions regarding making the amplifier stable.

regards
Darkseid

 

[jgk2004]

What is your load cap? Its only s single stage amplifier so it should definitely have more then 16 degrees of phase. Start with putting a load cap on it. Also just to let you know, you are missing half of your differential gain. You only have one path from each of your diff pairs (nmos pnmos) to your output. You are missing your current mirror which mirrors the other side of the diff structure to the output! Maybe this is causing your low phase margin.... Get ride of those current sources on the right and make it a cascode structure with mirror on top and bias the bottom from the far left over to the cascode structure on right. Unless ofcourse this is how you really want the structure......

Jgk

 

[darkseid]

Hi

Thanks for the suggestion. I tried placing a 10pF cap at the load . The phase margin is going up to 48 degrees but the bandwidth is really getting messed up. Also I am not able to understand the second part you have mentioned regarding the single path from each of diff pair.

I am designing a rail to rail amplifier. Differential amp followed by a current summation circuit. I am using this topology of current mirror as it has the lowest o/p voltage (for maximum swing) and best current matching. I was getting 83 dB gain and 76 degree phase margin, when I am biasing P7, P8 and similar transistors using separate current source and diode connected MOS. I just wanted to reduce the number of current sources in the circuit which was why I used resistor to bias.

Please advice

regards
Darkseid

 

[jgk2004]

What I mean about the second part of my comment is that you are not summing all four diff inputs to the output See linked pdf

**broken link removed**

When looking at slide 5 you see what you should have. It isn't drawn the way I would prefer because they split up the cascode structure onto both sides. But if you look at slide 11 you will see what you have, drawn the way you have it, but with a second stage class AB output by using battery biasing. Just ignore that part. But you will see how you only feed into two cascode stacks not three like you have. Then you have a mirror on the bottom and vbias voltages on the top.

Also just a note, if you are interested in GM equalization this slide has alittle info on it.

Jgk

 

[darkseid]

Hi

Thanks. Its working now.