[SOLVED] (URGENT) DLL SDF back annotation issue

[davitgh]

Hi Guys!

In my DLL design I have 1 input clk which shifted to clk_90, clk_180, clk_270 clocks.
During SDF annotation "timing_sense : positive_unate" arc delays do not propagate properly into outputs, in other wards
when I have "input clk rise" -> "output clk_90 rise" delay in SDF file it becomes "input clk rise" -> "output clk_90 fall" delay during SDF back-annotation.

Can you help to resolve this issue?

Regards,
Davit Gh.

 

[davitgh]

Hi Guys,

I solved the issue by adding simple model login in my gate level simulations.

Regards,
Davit Gh.