Urgent: about a compilation problem in QuartursII 5.0

[ethan]

design does not contain any logic

Dear Everybody,

I have a quick question about the compiation problem in Quarturs II 5.0. After I create a testbench to test LFSR, I always get the errors said:

"Error: Can't synthesize current design -- design does not contain any logic
......"

But, actually, the LFSR has been instantiated inside the testbench as a component and port mapped. And both LFSR_generic and LFSR_testbench are in the project named lfsr_testbench.

I don't why it kept complianing this problem. Anyone give me some ideas?

I have used MaxPlusII several years ago and this is the first time I use Quarturs.

I attach my vhdl code here.

Many thanks.

 

[echo47]

lfsr_testbench

This isn't an answer, but maybe it'll be helpful ...

Your HDL seems ok. LFSR_GENERIC synthesizes and routes fine in Xilinx ISE 8.1. Sorry that I don't have QuartusII to try.
Be sure you aren't accidentally synthesizing the testbench.

 

[nand_gates]

If ur trying to synthesize the testbench you will get the ERROR. Because ur
testbench does not have any input/output pins. I think you want to sythesize
the lfsr along with its testbench?? Then this is not the correct way of doing it.
Ur testbench should have clk, reset as inputs and test_status pin as output to
indicate test status. Ur current testbench is not synthesizable. You can not
generate clock inside FPGA!!

 

[vcnvcc]

I think u are taking vhdl design file as a test bench..