1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
| reg clk;
reg rst;
reg [383:0] tv[512:0];
wire [383:0] tmp;
reg kld;
wire [127:0] key, plain, ciph;
wire [127:0] text_in;
wire [127:0] text_out;
wire [127:0] text_out2;
reg [127:0] text_exp;
wire done, done2;
integer n, error_cnt;
initial
begin
kld = 0;
clk = 0;
rst = 0;
error_cnt = 0;
repeat(4) @(posedge clk);
rst = 1;
repeat(20) @(posedge clk);
tv[0]= 384'h000000000000000000000000000000009798c4640bad75c7c3227db910174e72a9a1631bf4996954ebc093957b234589;
tv[1]= 384'h0000000000000000000000000000000096ab5c2ff612d9dfaae8c31f30c42168ff4f8391a6a40ca5b25d23bedd44a597;
for(n=0;n<1;n=n+1)
begin
@(posedge clk);
#1;
kld = 1;
@(posedge clk);
#1;
kld = 0;
@(posedge clk);
while(!done) @(posedge clk);
if(text_out != ciph | (|text_out)==1'bx)
begin
error_cnt = error_cnt + 1;
end
while(!done2) @(posedge clk);
if(text_out2 != plain | (|text_out2)==1'bx)
begin
error_cnt = error_cnt + 1;
end
@(posedge clk);
#1;
end
repeat(10) @(posedge clk);
end
assign tmp = tv[n];
assign key = kld ? tmp[383:256] : 128'hx;
assign text_in = kld ? tmp[255:128] : 128'hx;
assign plain = tmp[255:128];
assign ciph = tmp[127:0];
always #5 clk = ~clk;
aes_cipher_top u0(
.clk( clk ),
.rst( rst ),
.ld( kld ),
.done( done ),
.key( key ),
.text_in( text_in ),
.text_out( text_out )
);
aes_inv_cipher_top u1(
.clk( clk ),
.rst( rst ),
.kld( kld ),
.ld( done ),
.done( done2 ),
.key( key ),
.text_in1( text_out ),
.text_out( text_out2 )
);
assign y=text_out2;
endmodule |