Unsupported Event Control Statement

[darshankumar]

hello every one,I have written a code for AES using verilog .I am getting desired output in model sim with the same code.I have to dump on FPGA .In order i am using xilinx 10.1,it is giving error and the code is below.
module test(output[127:0]y,input clk1);

---

Code Verilog - [expand]
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reg     clk;
reg     rst;
 
reg [383:0] tv[512:0];  
wire    [383:0] tmp;
reg     kld;
wire    [127:0] key, plain, ciph;
wire    [127:0] text_in;
wire    [127:0] text_out;
wire    [127:0] text_out2;
reg [127:0] text_exp;
wire        done, done2;
integer     n, error_cnt;
 
initial
   begin
  kld = 0;
  clk = 0;
  rst = 0;
  error_cnt = 0;
  
  repeat(4) @(posedge clk);
  rst = 1;
  repeat(20)    @(posedge clk);
 
tv[0]= 384'h000000000000000000000000000000009798c4640bad75c7c3227db910174e72a9a1631bf4996954ebc093957b234589;
tv[1]= 384'h0000000000000000000000000000000096ab5c2ff612d9dfaae8c31f30c42168ff4f8391a6a40ca5b25d23bedd44a597;
 
 
for(n=0;n<1;n=n+1)
   begin
  @(posedge clk);
  #1;
  kld = 1;
  @(posedge clk);
  #1;
  kld = 0;
  @(posedge clk);
 
  while(!done)  @(posedge clk);
if(text_out != ciph | (|text_out)==1'bx)
     begin
    error_cnt = error_cnt + 1;
     end
 
 
  while(!done2) @(posedge clk);
 
 
 
  if(text_out2 != plain | (|text_out2)==1'bx)
     begin
    error_cnt = error_cnt + 1;
     end
 
  @(posedge clk);
  #1;
   end
repeat(10)  @(posedge clk);
  
end
assign tmp = tv[n];
assign key     = kld ? tmp[383:256] : 128'hx;
assign text_in = kld ? tmp[255:128] : 128'hx;
assign plain   = tmp[255:128];
assign ciph    = tmp[127:0];
 
always #5 clk = ~clk;
 
aes_cipher_top u0(
  .clk(     clk     ),
  .rst(     rst     ),
  .ld(      kld     ),
  .done(        done        ),
  .key(     key     ),
  .text_in( text_in     ),
  .text_out(    text_out    )
  );
 
aes_inv_cipher_top u1(
  .clk(     clk     ),
  .rst(     rst     ),
  .kld(     kld     ),
  .ld(      done        ),
  .done(        done2       ),
  .key(     key     ),
  .text_in1(    text_out    ),
  .text_out(    text_out2   )
  );
assign y=text_out2;
 
endmodule

---

The errors displaying are...

ERROR:Xst:850 - "asasd.v" line 24: Unsupported Event Control Statement. 
ERROR:Xst:850 - "asasd.v" line 24: Unsupported Event Control Statement. 
ERROR:Xst:850 - "asasd.v" line 24: Unsupported Event Control Statement. 
ERROR:Xst:850 - "asasd.v" line 24: Unsupported Event Control Statement. 
ERROR:Xst:850 - "asasd.v" line 26: Unsupported Event Control Statement. 
ERROR:Xst:850 - "asasd.v" line 26: Unsupported Event Control Statement. 
ERROR:Xst:850 - "asasd.v" line 26: Unsupported Event Control Statement. 
ERROR:Xst:850 - "asasd.v" line 26: Unsupported Event Control Statement. 
ERROR:Xst:850 - "asasd.v" line 26: Unsupported Event Control Statement. 
ERROR:Xst:850 - "asasd.v" line 26: Unsupported Event Control Statement. 
ERROR:Xst:850 - "asasd.v" line 26: Unsupported Event Control Statement. 
ERROR:Xst:850 - "asasd.v" line 26: Unsupported Event Control Statement. 
ERROR:Xst:850 - "asasd.v" line 26: Unsupported Event Control Statement. 
ERROR:Xst:850 - "asasd.v" line 26: Unsupported Event Control Statement. 
ERROR:Xst:850 - "asasd.v" line 26: Unsupported Event Control Statement. 
ERROR:Xst:850 - "asasd.v" line 26: Unsupported Event Control Statement. 
ERROR:Xst:850 - "asasd.v" line 26: Unsupported Event Control Statement. 
ERROR:Xst:850 - "asasd.v" line 26: Unsupported Event Control Statement. 
ERROR:Xst:850 - "asasd.v" line 26: Unsupported Event Control Statement. 
ERROR:Xst:850 - "asasd.v" line 26: Unsupported Event Control Statement. 
ERROR:Xst:850 - "asasd.v" line 26: Unsupported Event Control Statement. 
ERROR:Xst:850 - "asasd.v" line 26: Unsupported Event Control Statement. 
ERROR:Xst:850 - "asasd.v" line 26: Unsupported Event Control Statement. 
ERROR:Xst:850 - "asasd.v" line 26: Unsupported Event Control Statement. 
ERROR:Xst:2634 - "asasd.v" line 32: For loop stop condition should depend on loop variable or be static.
ERROR:Xst:850 - "asasd.v" line 61: Unsupported Event Control Statement. 
ERROR:Xst:850 - "asasd.v" line 61: Unsupported Event Control Statement. 
ERROR:Xst:850 - "asasd.v" line 61: Unsupported Event Control Statement. 
ERROR:Xst:850 - "asasd.v" line 61: Unsupported Event Control Statement. 
ERROR:Xst:850 - "asasd.v" line 61: Unsupported Event Control Statement. 
ERROR:Xst:850 - "asasd.v" line 61: Unsupported Event Control Statement. 
ERROR:Xst:850 - "asasd.v" line 61: Unsupported Event Control Statement. 
ERROR:Xst:850 - "asasd.v" line 61: Unsupported Event Control Statement. 
ERROR:Xst:850 - "asasd.v" line 61: Unsupported Event Control Statement. 
ERROR:Xst:850 - "asasd.v" line 61: Unsupported Event Control Statement.

Please help me ....

 

[FvM]

The code looks like a testbench that has been hastily supplemented with a clock input and an output signal. But the clock input is unconnected and the design miles away from synthesizable Verilog.

Start with a specification of in- and outputs and intended design function.

 

[sagar.m]

Your code is not at all synthesizable .First of all refer the guideline for synthesis of verilog code and one more thing modelsim is just simulator so it will not tell which component can be synthesize and it cannot distinguish between design module and test-bench it will simulate your program like a programming language compiler