raguna
Junior Member level 3
Hi all!
I am trying to design an ALU which does signed addition & subtraction and unsigned addition & subtraction. I have following code written, but does not work.
For unsigned : I used simple R<= A+B and R<= A-B; for addition and subtraction
For Signed: I tried to change the type of A,B to Signed and perform addition. And I am not sure how to check for overflow/underflow. Can someone please help me in this?
I am trying to design an ALU which does signed addition & subtraction and unsigned addition & subtraction. I have following code written, but does not work.
For unsigned : I used simple R<= A+B and R<= A-B; for addition and subtraction
For Signed: I tried to change the type of A,B to Signed and perform addition. And I am not sure how to check for overflow/underflow. Can someone please help me in this?
Code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity lab5 is
port(CLK: in std_logic;
A,B : in std_logic_vector(15 downto 0);
R : out std_logic_vector(15 downto 0);
Overflow : out std_logic);
end lab5;
architecture archi of lab5 is
signal tmp : std_logic_vector( 16 downto 0);
variable sgnA, sgnB : SIGNED (16 downto 0);
variable sgnout : SIGNED (16 downto 0);
variable usgnA, usgnB: UNSIGNED (16 downto 0);
variable usgnout : UNSIGNED (16 downto 0);
begin
process (CLK)
begin
sgnA := signed(A'high+1 downto 0);
sgnB := signed(B'high+1 downto 0);
usgnA := unsigned(A);
usgnB := unsigned(B);
if (CLK'event and CLK='1') then
if(AluOp = "00000") then
{R <= A + B; --Unsigned addition
Overflow <= A(15) and B(15);}
elsif(AluOp = "00001") then
{R <= A-B; --treating A & B as unsigned integers
Overflow <= (A<B)?1:0; -- For underflow case }
elsif(AluOp = "00010") then
{sgnout=sgnA-sgnB;--treating A & B as unsigned integers
R <= std_logic_vector(sgnout); --Not sure how to do overflow in signed}
elsif(AluOp = "00011") then
{sgnout=sgnA-sgnB;--treating A & B as unsigned integers
R <= std_logic_vector(sgnout); }
Last edited: