library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity lab5 is
port(CLK: in std_logic;
A,B : in std_logic_vector(15 downto 0);
R : out std_logic_vector(15 downto 0);
Overflow : out std_logic);
end lab5;
architecture archi of lab5 is
signal tmp : std_logic_vector( 16 downto 0);
variable sgnA, sgnB : SIGNED (16 downto 0);
variable sgnout : SIGNED (16 downto 0);
variable usgnA, usgnB: UNSIGNED (16 downto 0);
variable usgnout : UNSIGNED (16 downto 0);
begin
process (CLK)
begin
sgnA := signed(A'high+1 downto 0);
sgnB := signed(B'high+1 downto 0);
usgnA := unsigned(A);
usgnB := unsigned(B);
if (CLK'event and CLK='1') then
if(AluOp = "00000") then
{R <= A + B; --Unsigned addition
Overflow <= A(15) and B(15);}
elsif(AluOp = "00001") then
{R <= A-B; --treating A & B as unsigned integers
Overflow <= (A<B)?1:0; -- For underflow case }
elsif(AluOp = "00010") then
{sgnout=sgnA-sgnB;--treating A & B as unsigned integers
R <= std_logic_vector(sgnout); --Not sure how to do overflow in signed}
elsif(AluOp = "00011") then
{sgnout=sgnA-sgnB;--treating A & B as unsigned integers
R <= std_logic_vector(sgnout); }
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_SIGNED.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ALU16 is port
( A: in std_logic_vector (15 downto 0);
B: in std_logic_vector (15 downto 0);
AluOp: in std_logic_vector (4 downto 0);
shamt: in std_logic_vector (2 downto 0);
Zero: out std_logic;
Overflow: out std_logic;
R: out std_logic_vector (15 downto 0)
);
end ALU16;
architecture RTL of ALU16 is
signal temp : std_logic_vector( 16 downto 0);
signal usgnA, usgnB, Reg1 : unsigned(15 downto 0);
signal sgnA, sgnB, Reg2 : signed(15 downto 0);
begin
process(AluOp)
variable p : integer range 0 to 15;
begin
--usgnA <= unsigned(A);
--usgnB <= unsigned(B);
sgnA <= signed(A);
sgnB <= signed(B);
case AluOp is
when "00000" =>
--Reg1 <= usgnA + usgnB;
temp <= ('0' & A) + ('0' & B);
Overflow <= temp(16);
--temp <= A + B;
R<=temp(15 downto 0);
--Overflow <= A(15) and B(15);
-- when "00001" =>
-- --Reg1 <= usgnA - usgnB;
-- R<=A-B;
-- if (A < B) then Overflow<= '1';
-- else Overflow<= '0';
-- end if;
--
-- when "00010" =>
-- Reg2 <= sgnA + sgnB;
-- R<=std_logic(Reg2);
-- Overflow <= A(14) and B(14);
--
-- when "00011" =>
-- R <= sgnA - sgnB;
-- R<=std_logic(Reg2);
-- if (sgnA < sgnB) then Overflow<= '1';
-- else Overflow<= '0';
-- end if;
--
-- when "00100" =>
-- if(A < B) then
-- R <= "1111111111111111";
-- else
-- R<= "0000000000000000";
-- end if;
-- when "00101" =>
-- for i in 0 to 15 loop
-- R(i)<= A(i) and B(i);
-- end loop;
--
-- when "00110" =>
-- for i in 0 to 15 loop
-- R(i)<= A(i) or B(i);
-- end loop;
--
--
-- when "00111" =>
-- for i in 0 to 15 loop
-- R(i)<= not (A(i) or B(i));
-- end loop;
--
--
-- when "01000" =>
-- for i in 0 to 15 loop
-- R(i)<= (A(i) xor B(i));
-- end loop;
--
-- when "01001" =>
-- for i in 0 to 15 loop
-- R(i)<= not A(i);
-- end loop;
--
-- when "01010" =>
-- temp <= A;
-- temp <= shift_left(A,to_integer(shamt));
-- p :=to_integer(shamt);
-- for i in 1 to 3 loop
-- temp(i-1) <= '0';
-- end loop;
-- R<= temp;
--
--
-- when "01011" =>
-- temp <= A;
-- temp <= shift_right(A,to_integer(shamt));
-- p :=to_integer(shamt);
-- for i in 1 to 3 loop
-- temp(i-1) <= '0';
-- end loop;
-- R<= temp;
--
-- when "01100" =>
-- temp <= A;
-- temp <= shift_right(A,to_integer(shamt));
-- p :=to_integer(shamt);
-- for i in 1 to 3 loop
-- temp(i-1) <= A(15);
-- end loop;
-- R<= temp;
when others =>
NULL;
-- if( R = "0000000000000000" ) then
-- Zero <= '1';
-- else Zero <='0';
-- end if;
end case;
end process;
end RTL;
According to your second case the first case output should be 255 check once.Actually 253 (binary) is the 2's complement of 3 which is equal to -3.better change radix representation to signed in your simulation.the output should be -1.. but i got 1.
and if i change variable a into 3 and variable b into 9 the output from simulation is 253.. it should be -3
may someone help me
According to your second case the first case output should be 255 check once.Actually 253 (binary) is the 2's complement of 3 which is equal to -3.better change radix representation to signed in your simulation.
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