Universal shift register (load state and serial data confusion)

[sarjumaharaj]

Have a look at the image i have attached. It is an example of universal shift register. It was in one of the sections of parallel in parellel out universal shift register. However, I think that this USR can do serial input as well with it's SR and SL inputs. Can anyone please see and tell me.

Also, for the load and gate, one of the port is connected to the rightshift on signal LR. Is it important that we do that, or is it necessary at all?

 

[Analog Ground]

Sorry but I am not sure what is your question. However, I think the connection of L/R input needs to be removed from the "LOAD" AND gates. Everything else looks OK. Perhaps there is one function missing. This design will do something on every clock. You might want to add a "HOLD" function which freezes the register contents. The functions are then SR, SL, LOAD and HOLD. Then, what about a RESET or CLEAR?