r1caw ex ua6bqg
Member level 2
Hi all!
After place-and-route in the Synopsys ICC I have timing report for some worst path. For example, it looks similar like this:
Name.........Reference.....Type..... Cap........Trans ...others results...
/DFF/CP.......DFF12LVT.......in.......0.0013....0.100
/DFF/Q........DFF12LVT......out......0.0000....0.038
/n46................net.....................0.0645
/AND/A2.......AND4LVT.......in.......0.0019....0.107
/AND/Z.........AND4LVT......out......0.0000....0.039
/n22................................net.....0.0035
/OR/A2.........AND4LVT........in......0.0010....0.039
/OR/Z...........AND4LVT.......out.....0.0000....0.032
So, the question is: why in some cases output and input transition time for two nets (out and in) connected to the similar net are equal, and in some cases they are unequal? I thought for any source and sink pins connected together transition time must be equal, but now I am little bit confused.
Thank you!
After place-and-route in the Synopsys ICC I have timing report for some worst path. For example, it looks similar like this:
Name.........Reference.....Type..... Cap........Trans ...others results...
/DFF/CP.......DFF12LVT.......in.......0.0013....0.100
/DFF/Q........DFF12LVT......out......0.0000....0.038
/n46................net.....................0.0645
/AND/A2.......AND4LVT.......in.......0.0019....0.107
/AND/Z.........AND4LVT......out......0.0000....0.039
/n22................................net.....0.0035
/OR/A2.........AND4LVT........in......0.0010....0.039
/OR/Z...........AND4LVT.......out.....0.0000....0.032
So, the question is: why in some cases output and input transition time for two nets (out and in) connected to the similar net are equal, and in some cases they are unequal? I thought for any source and sink pins connected together transition time must be equal, but now I am little bit confused.
Thank you!