One problem seen during breadboarding and testing the circuit was that
the FET was causing large voltage drops (7 or 8 Volts) in the 12 Volt power
bus whenever it turned on. Upon looking at the ID-VDS characteristic curve,
it was seen that whenever the FET was on, it would draw currents greater
than 3 Amps, which was the current limit on the power supply. This forces
the power supply out of its linear region of operation and the voltage drops
signiØcantly. As the FET switches on and oÆ with the PWM input, a large
ripple eÆect is created in the 12 Volt line.
One way to reduce the size of the ripple in the power line is to use
a diÆerent FET with a higher on resistance and a lower magnitude ID-VDS
curve. The new FET brings a signiØcant improvement to the circuit. It cleaned
up the 12 Volt bus and also increased the output voltage by 50 Volts peak-
to-peak. There was still, however, a small 2 to 3 Volt ripple that occurred
whenever the FET was being switched on and oÆ. As it turned out, this
was caused by the breadboard. The problem with using breadboards is that
the connections become very unreliable with high frequencies or high current
designs because the spring clips inside the breadboard have a small contact area
and can overheat quite easily. These white breadboards are only recommended
for circuits using less than 100 mA, but this part of the transmitter circuit
uses several Amps of current. Because of the high current in this design, the
resistance seen from the path connected to the 10uF capacitor became a good
amount larger than the path going to the power supply, so instead of tapping
the stored current in the capacitor, the FET was forcing current from the
power supply. To Øx this problem, a small 10 Ohm resistor is added between
the primary of the transformer and the 12 Volt bus to force the FET to use
the stored current in the low impedance capacitor before taking it from the
power supply. This addition smoothed the ripple from the 12 Volt line.