Hi guys,
I still have some troubles in the design.
I made the circuit like this:
*
* Component pathname : $MGC_WD/ota_cascode_dobrado
*
.subckt OTA_CASCODE_DOBRADO VO VDD VI+ VI- VSS
.CONNECT VSS VSS
.CONNECT VDD VDD
MN3 N$39 N$39 VSS VSS n L=2u W=52u
MP5 N$217 N$217 VDD VDD p L=2u W=306u
I1 VSS N$225 DC 200uA
MN11 N$204 N$169 VSS VSS n L=2u W=306u
MN10 N$218 N$225 N$204 VSS n L=2u W=306u
MN9 N$169 N$169 VSS VSS n L=2u W=306u
MN8 N$225 N$225 N$169 VSS n L=2u W=306u
MP2 N$54 N$217 VDD VDD p L=2u W=153u
MP1 N$53 N$217 VDD VDD p L=2u W=153u
MN7 N$7 N$169 VSS VSS n L=2u W=306u
MN6 N$54 VI- N$7 VSS n L=2u W=153u
MN5 N$53 VI+ N$7 VSS n L=2u W=153u
MN4 N$41 N$39 VSS VSS n L=2u W=52u
MN2 VO N$33 N$41 VSS n L=2u W=52u
MN1 N$33 N$33 N$39 VSS n L=2u W=52u
MP6 N$218 N$218 N$217 VDD p L=2u W=306u
MP3 N$33 N$218 N$53 VDD p L=2u W=52u
MP4 VO N$218 N$54 VDD p L=2u W=52u
.ends OTA_CASCODE_DOBRADO
And I obtained the open loop response like this:
In the fig is showed my design and the ideal. You can see that the phase of my design is very different from an ideal.
How can I solve this?
Thanks.