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Understanding the design of a folded cascode OTA

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brito.tb

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Hi,

I am studying how to design an OTA, as reference I am using the book CMOS Analog Circuit Design from Allen. But I have some questions that isn't explained in the book. How can I calculate the bias voltages showed in this figure?

Captura_da_tela-6.png

Thanks
 

BradtheRad

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The diagram illustrates concept of operation. The icons are enhancement mode which is more commonly used than depletion mode.

N-channel mosfets are the ones with the arrow in the lower leg (or source terminal). So this means you would apply input voltages ranging between zero and +5v to operate their gates. Gate V is referenced to source terminal.

If you apply 0V to the gate it will cause the mosfet to show high impedance across source and drain terminals.

If you apply 5V or more to the gate it will cause the mosfet to be 0.1 ohm or so.

Adjust proportionately for figures in between.

As for the P-mosfets they are identified by the arrow in the upper leg (or drain terminal). So you would apply between VDD and VDD-5 to operate their gates. Gate V is referenced to the drain terminal.

Say the VDD is 12V. Then the P-channel mosfets operate on gate voltages from 7V to 12V.

Apply 12 V to the gate and it causes the mosfet to show high resistance.

Apply 7V or less to the gate and it causes the mosfet to be 0.1 ohm.

Adjust proportionately for figures in between.

These are ballpark figures of operation.
 

javadamirpoor

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Hi,

I am studying how to design an OTA, as reference I am using the book CMOS Analog Circuit Design from Allen. But I have some questions that isn't explained in the book. How can I calculate the bias voltages showed in this figure?

View attachment 56831

Thanks
hi.
what is ota?
 

brito.tb

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The diagram illustrates concept of operation. The icons are enhancement mode which is more commonly used than depletion mode.

N-channel mosfets are the ones with the arrow in the lower leg (or source terminal). So this means you would apply input voltages ranging between zero and +5v to operate their gates. Gate V is referenced to source terminal.

If you apply 0V to the gate it will cause the mosfet to show high impedance across source and drain terminals.

If you apply 5V or more to the gate it will cause the mosfet to be 0.1 ohm or so.

Adjust proportionately for figures in between.

As for the P-mosfets they are identified by the arrow in the upper leg (or drain terminal). So you would apply between VDD and VDD-5 to operate their gates. Gate V is referenced to the drain terminal.

Say the VDD is 12V. Then the P-channel mosfets operate on gate voltages from 7V to 12V.

Apply 12 V to the gate and it causes the mosfet to show high resistance.

Apply 7V or less to the gate and it causes the mosfet to be 0.1 ohm.

Adjust proportionately for figures in between.

These are ballpark figures of operation.
Thanks for the answer BradtheRad, but my really doubt is about how to calculate the bias voltages like Vnb1, Vnb2, Vpb1 e Vpb2. I already calculated the sizes of the transistors following the book of Allen. But there isn't explain how to calculate the bias voltages. Anyone knows how to?
 

BradtheRad

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Thanks for the answer BradtheRad, but my really doubt is about how to calculate the bias voltages like Vnb1, Vnb2, Vpb1 e Vpb2. I already calculated the sizes of the transistors following the book of Allen. But there isn't explain how to calculate the bias voltages. Anyone knows how to?
This could be a case where the author presupposes certain prior knowledge on the part of the reader.

Or that the reader is acquainted with his previous books.(Authors love it when you buy their books.)

Or else the author will explain operation in a later chapter.

Or in a later book. (Authors love it when you buy their books.)

Since the circuit is introduced now then it may be primarily so you can spot what the text calls attention to now.

Other than that there are a few obvious things we can notice:

(a) a similar transconductance amp could be made using transistors instead of mosfets.

(b) there's what looks like a current mirror construction at left.

(c) R_out is printed to emphasize something to do with resistance... and that probably has to do with available current, since it's a transconductance ampllifier.

(d) the output will be high-impedance unless some kind of pulse or signal comes in at Vpb1 and Vpb2 and/or Vnb2,

(e) output will source current (will go positive) to the extent Vpb1 and Vpb2 are brought low.

(f) output sinks current (will go to ground) to the extent Vnb2 is brought high.

Etc.
 

ella1923

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Use simple MOS characteristic equations like Vds>Vgs-Vth, Id =1/2uC(W/L)(Vgs-Vth)^2. along with it, you can approximately identify transistor sizes.You can refer book of razavi too.
 

brito.tb

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Hi guys,

I still have some troubles in the design.
I made the circuit like this:

*
* Component pathname : $MGC_WD/ota_cascode_dobrado
*
.subckt OTA_CASCODE_DOBRADO VO VDD VI+ VI- VSS

.CONNECT VSS VSS
.CONNECT VDD VDD
MN3 N$39 N$39 VSS VSS n L=2u W=52u
MP5 N$217 N$217 VDD VDD p L=2u W=306u
I1 VSS N$225 DC 200uA
MN11 N$204 N$169 VSS VSS n L=2u W=306u
MN10 N$218 N$225 N$204 VSS n L=2u W=306u
MN9 N$169 N$169 VSS VSS n L=2u W=306u
MN8 N$225 N$225 N$169 VSS n L=2u W=306u
MP2 N$54 N$217 VDD VDD p L=2u W=153u
MP1 N$53 N$217 VDD VDD p L=2u W=153u
MN7 N$7 N$169 VSS VSS n L=2u W=306u
MN6 N$54 VI- N$7 VSS n L=2u W=153u
MN5 N$53 VI+ N$7 VSS n L=2u W=153u
MN4 N$41 N$39 VSS VSS n L=2u W=52u
MN2 VO N$33 N$41 VSS n L=2u W=52u
MN1 N$33 N$33 N$39 VSS n L=2u W=52u
MP6 N$218 N$218 N$217 VDD p L=2u W=306u
MP3 N$33 N$218 N$53 VDD p L=2u W=52u
MP4 VO N$218 N$54 VDD p L=2u W=52u
.ends OTA_CASCODE_DOBRADO

And I obtained the open loop response like this:
resposta_malha_aberta.jpg

In the fig is showed my design and the ideal. You can see that the phase of my design is very different from an ideal.
How can I solve this?
Thanks.
 

leo_o2

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For practical ota, there is other parasite zeroes and poles that causes different phase characteristic.
 

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