Arturi
Member level 2
Dear all,
I have a piece of code that describes a 13-bit flip-flop being reset to a 10-bit pattern:
reg [`MSB20:0] reg20;
always @(posedge clk or negedge rstb_regs)
if (~rstb_regs)
reg20 <= 10'b00_1000_0000;
else
......
In simulation I see that bits 13:10 are reset to zero.
But what happens in synthesis??? Do the most significant register are synthesized to flops with asynchronous reset?? Or the tool chooses plain flops which have less area?? After all we are not specifying a reset value for these flops...
Thanks,
Arturi
I have a piece of code that describes a 13-bit flip-flop being reset to a 10-bit pattern:
reg [`MSB20:0] reg20;
always @(posedge clk or negedge rstb_regs)
if (~rstb_regs)
reg20 <= 10'b00_1000_0000;
else
......
In simulation I see that bits 13:10 are reset to zero.
But what happens in synthesis??? Do the most significant register are synthesized to flops with asynchronous reset?? Or the tool chooses plain flops which have less area?? After all we are not specifying a reset value for these flops...
Thanks,
Arturi