Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Uncertainty - how to arive at an Exact equation? (is it just skew + jitter + OCV )

Status
Not open for further replies.

hariharan.gb

Junior Member level 1
Junior Member level 1
Joined
Feb 2, 2012
Messages
17
Helped
3
Reputation
6
Reaction score
3
Trophy points
1,283
Location
Bangalore, India, India
Visit site
Activity points
1,430
To my knowledge -

Uncertainty - the equation comprises addition of

( Jitter + Tool delta Uncertainty + skew (for prelayout) + OCV + few percent of wireload)

+++++++++++++++++++++++++++++++++++++++

Assuming we can have a 5 - 10 % of clock for Jitter.

Can anyone please tell me how this skew is calculated, with clock as reference ?

Flat percentage of value we can have for skew, but then there is a formula to arrive for any skew. Can anyone share it?


OCV and wireload delay are meager value, which I shall raise a seperate discussion post :p

Hariharan GB

- - - Updated - - -

To add more for skew calculation:

Skew parameters comprises attributes like ( Rise/fall transition of clock, frequency parameter, Flip flop counts etc)

Can anyone get me a theoretical equation to arrive with all the above mentioned parameter to get a perfect skew calculation ?

Hariharan GB
 

Hi Guys,

Please help me., like how can we make a generic equation to skew, considering all type of clock frequencies.

Skew = x + y + z .... ?

Thanks
Hariharan GB
 

HI Hariharan,

Suppose two flops are there one is launch flop another is capture flop,
Clock Skew is defined as difference between clock arrival times between launch and capture flops.
What are the factors are involved for calculating the skew ::

In pll some jitter is available
from pll to clock root pin source latency + ocv effect
from clock root pin to flops network latency
now skew = (jitter + source latency + ocv effect +network latency (between clock root pin to launch flop/capture flop) - (jitter +source latency +ocv effect + network latency (between clock root pin to capture flop/ launch flop)
Latency values are calculated based on wire load models or real spef's based on which stage you need to calculate the skew.
Hope you understand.
 
  • Like
Reactions: hjacky

    hjacky

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top