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Unable to run the simulation correctly ( Modelsim )

bravo1234

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Please find the attached simulation and required verilog files (notepad).
If you see the simulation ,you would notice 00x values as output and it is in red. It is expected that the output is 3 bit number instead of 00x. I am unable to rectify the problem. (Modelsim starter edition)

I have tried to make sure
1. The port connections between modules is right.
2. wire declarations
3.Checked the output of individual modules its perfect.

Please help.
simulation results.jpgView attachment Pulse_detector.txtView attachment Axel_final_count.txtView attachment Uni_D.txt
 

std_match

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In pulse_detector, you assign values to event_pcounter in two different always blocks. When they assign different values you get the 'x' in simulation.
Only assign from one always block.
 

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Please use code tags from now on I don't like having to download files to read code.

This is probably not synthesizable code or will synthesize to something that doesn't work like you expect.
Besides the event_pcounter being in two different always blocks you also have generated a latch by using the event_pulse as a level sensitive signal to the second always block. You will probably have problems with the event_pcounter once this is synthesized.

You also have a #1 delay in your synthesizable code, which is useless. If it is needed for the simulation to work correctly then that just proves that the code isn't written correctly.

In Axel_final_count you have a large combonational circuit that is supposed to have an embedded counter. You've just generated a large latch structure that won't synthesize to a working counter.

This code needs to be completely rewritten. You need to learn the difference between writing asynchronous and synchronous code. Due to the issues with FPGA routing and timing writing asynchronous code in an FPGA is fraught with issues. You should always write synchronous code if you want reliable results in an FPGA.
 

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