unable override param in VCS

[jgreninger]

I have a parameter to override that works great in Incisive using -defparam. I'm unable to find an equivalent that works in VCS. Here are the ones I've tried

1. +gfile <file>

• the override file contains
• assign "new_value_as_string" <path_to_param_to_override>

2. -pvalue <path_to_param>=newvalue

PVALUE doesn't work because it doesn't accept string, so that leaves me with GFILE. GFILE compiles and runs but the PARAM value remains the same and it loads the incorrect initialization file for an array in the testbench

Does anyone know of a working method in VCS that will actually override a file path like -defparam does but in VCS?

Thanks,

John

 

[jgreninger]

I should mention this is a Verilog design but -gfile requires the hierarchy be in VHDL. The hierarchy has a generate array in it as well (which the section on -gfile says you need to use "rounded" parentheses for). So...my hierarchy path is

/top/dut(5)/mymodel/mysubmodel/myparameter