Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity pulse_tx is port( clock_50 : in std_logic; GPIO_0 : inout std_logic_vector(35 downto 0) ); end pulse_tx; architecture arch of pulse_tx is type state_type is (init, write_state, idle_state); signal state : state_type := init; signal clock_5 : std_logic := '0'; signal clk_div : integer range 0 to 5 := 0; signal count : integer range 0 to 500000 := 0; begin -- GPIO_0(0) <= OE OF MD1213; -- GPIO_0(1) <= INA OF MD1213; -- GPIO_0(3) <= INB OF MD1213; GPIO_0(35 downto 4) <= (others => '0'); process(clock_50) -- CLOCK DIVISION PROCESS begin if(rising_edge(clock_50)) then if (clk_div = 4) then clock_5 <= clock_5 xor '1'; clk_div <= 0; else clk_div <= clk_div + 1; end if; end if; end process; process(clock_50) begin if(rising_edge(clock_5)) then if(clk_div= 4 and clock_5 = '1') then case state is when init => GPIO_0(0) <= '0'; GPIO_0(1) <= '0'; GPIO_0(3) <= '1'; if (count = 100) then count <= count + 1; state <= write_state; else count <= count + 1; state <= init; end if; when write_state => if (count > 100 and count < 250000) then count <= count + 1; if (count = 190000) then GPIO_0(0) <= '1'; state <= write_state; elsif(count = 200000) then GPIO_0(0) <= '1'; GPIO_0(1) <= '1'; state <= write_state; elsif(count = 200050) then GPIO_0(0) <= '1'; GPIO_0(1) <= '0'; GPIO_0(3) <= '0'; state <= write_state; elsif(count = 200100) then GPIO_0(0) <= '1'; GPIO_0(1) <= '1'; GPIO_0(3) <= '1'; state <= write_state; elsif(count = 200150) then GPIO_0(0) <= '1'; GPIO_0(1) <= '0'; GPIO_0(3) <= '0'; state <= write_state; elsif(count = 200200) then GPIO_0(0) <= '1'; GPIO_0(1) <= '1'; GPIO_0(3) <= '1'; state <= write_state; elsif(count = 200250) then GPIO_0(1) <= '0'; GPIO_0(0) <= '1'; GPIO_0(3) <= '0'; state <= write_state; elsif(count = 200300) then GPIO_0(1) <= '1'; GPIO_0(0) <= '1'; GPIO_0(3) <= '1'; state <= write_state; elsif(count = 200350) then GPIO_0(1) <= '0'; GPIO_0(0) <= '1'; GPIO_0(3) <= '0'; state <= write_state; elsif(count = 200400) then GPIO_0(1) <= '1'; GPIO_0(3) <= '1'; GPIO_0(0) <= '1'; state <= write_state; elsif(count = 200450) then GPIO_0(1) <= '0'; GPIO_0(0) <= '1'; GPIO_0(3) <= '0'; state <= write_state; elsif(count = 200500) then GPIO_0(0) <= '1'; GPIO_0(3) <= '1'; state <= write_state; else state <= write_state; end if; elsif(count = 250000) then count <= count + 1; state <= idle_state; end if; when idle_state => if(count > 250000 and count < 500000) then GPIO_0(0) <= '0'; if (count = 499999) then count <= 101; state <= write_state; else count <= count + 1; state <= idle_state; end if; end if; end case; end if; end if; end process; end arch;
Not to deviate from the topis of this thread,but i don't think it is an issue if generate clocks by using clocking wizard ip core which uses either pll or mmcm rather than gated clock.why do you have a generated clock? They are very bad practice on FPGAs, it can cause all sorts of timing problems - you should look into using clock enables instead.
Not to deviate from the topis of this thread,but i don't think it is an issue if generate clocks by using clocking wizard ip core which uses either pll or mmcm rather than gated clock.
Some people constraint the gated clock to use clock signal routing resources that ensure low skew delivery rather than normal logic signal routing resources.But i don't know if doing this a good practice ?
Yeah i saw his code & knew that he was using logic generated clocks.Did you even look at the OP's code?
They generate a clock using a divider implemented in LUT-FF logic.
Using logic generated clocks is bad practice - its much harder to control the timing/skew
can you please post the way you want me to implement clock using clock enables.
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 process(clk) begin if rising_edge(clk) then enable <= not enable; if enable = '1' then --stuff in here runs at clk/2 end if; end if; end process;
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 -- divide by 4 enable process (clk, rst) begin if (rst = '1') then -- async reset count <= 0; enable <= '0'; elsif rising_edge(clk) then count <= count + 1; if (count = 3) then enable <= '1'; else enable <= '0'; end if; end if; begin end process; -- process running at clk, but only enabled every clk/4. process (clk) begin if rising_edge(clk) then if (rst = '1') then -- synchronous reset -- reset values elsif (enable) then -- do this stuff every clock cycle when enabled end if; end if; end process;
This is another important point - why do you have a generated clock? They are very bad practice on FPGAs, it can cause all sorts of timing problems - you should look into using clock enables instead."
can you please post the way you want me to implement clock using clock enables.
-- vhdl
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- entity declaration
architecture dancing is
signal counter : natural range 0 to 3 := 0;
signal clk_en : std_logic := '0';
begin
clockdivider : process (clock_50) is
begin
if rising_edge ( clock_50) then
counter <= (counter + 1) mod 4;
if (counter = 3) then
clk_en <= '1';
else
clk_en <= '0';
end if;
end if; -- clock edge
end process clockdivider;
-- use the clock enable whenever you need to do something at the sample frequency.
do_something : process (clock_50) is
begin
if rising_edge (clock_50) then
isEnabled : if clken = '1' then
-- ... do whatever
end if isEnabled;
end if; -- clock
end process do_something;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pulse_tx is
port(
clock_50 : in std_logic;
GPIO_0 : out std_logic_vector(35 downto 0)
);
end pulse_tx;
architecture arch of pulse_tx is
type state_type is (init, write_state, idle_state);
signal state : state_type := init;
signal clk_en : std_logic := '0';
signal counter : integer range 0 to 9 := 0;
signal count : integer range 0 to 500000 := 0;
begin
-- GPIO_0(0) <= OE OF MD1213;
-- GPIO_0(1) <= INA OF MD1213;
-- GPIO_0(3) <= INB OF MD1213;
GPIO_0(35 downto 4) <= (others => '0');
GPIO_0(2) <= clk_en;
process(clock_50) -- CLOCK DIVISION PROCESS
begin
if(rising_edge(clock_50)) then
counter <= counter + 1;
if (counter = 9) then
clk_en <= '1';
counter <= 0;
else
clk_en <= '0';
end if;
end if;
end process;
process(clock_50)
begin
if(rising_edge(clock_50)) then
if (clk_en = '1') then
case state is
when init =>
--count <= 0;
GPIO_0(0) <= '0';
GPIO_0(1) <= '0';
GPIO_0(3) <= '1';
if (count = 100) then
count <= count + 1;
state <= write_state;
else
count <= count + 1;
state <= init;
end if;
when write_state =>
if (count > 100 and count < 250000) then
count <= count + 1;
if (count = 190000) then
GPIO_0(0) <= '1';
state <= write_state;
elsif(count = 200000) then
GPIO_0(0) <= '1';
GPIO_0(1) <= '1';
--GPIO_0(3) <= '1';
--count <= count + 1;
state <= write_state;
elsif(count = 200050) then
GPIO_0(0) <= '1';
GPIO_0(1) <= '0';
GPIO_0(3) <= '0';
--count <= count + 1;
state <= write_state;
elsif(count = 200100) then
GPIO_0(0) <= '1';
GPIO_0(1) <= '1';
GPIO_0(3) <= '1';
--count <= count + 1;
state <= write_state;
elsif(count = 200150) then
GPIO_0(0) <= '1';
GPIO_0(1) <= '0';
GPIO_0(3) <= '0';
--count <= count + 1;
state <= write_state;
elsif(count = 200200) then
GPIO_0(0) <= '1';
GPIO_0(1) <= '1';
GPIO_0(3) <= '1';
--count <= count + 1;
state <= write_state;
elsif(count = 200250) then
GPIO_0(1) <= '0';
GPIO_0(0) <= '1';
GPIO_0(3) <= '0';
--count <= count + 1;
state <= write_state;
elsif(count = 200300) then
GPIO_0(1) <= '1';
GPIO_0(0) <= '1';
GPIO_0(3) <= '1';
--count <= count + 1;
state <= write_state;
elsif(count = 200350) then
GPIO_0(1) <= '0';
GPIO_0(0) <= '1';
GPIO_0(3) <= '0';
--count <= count + 1;
state <= write_state;
elsif(count = 200400) then
GPIO_0(1) <= '1';
GPIO_0(3) <= '1';
GPIO_0(0) <= '1';
--count <= count + 1;
state <= write_state;
elsif(count = 200450) then
GPIO_0(1) <= '0';
GPIO_0(0) <= '1';
GPIO_0(3) <= '0';
--count <= count + 1;
state <= write_state;
elsif(count = 200500) then
--GPIO_0(1) <= '0';
GPIO_0(0) <= '1';
GPIO_0(3) <= '1';
----count <= count + 1;
state <= write_state;
else
--count <= count + 1;
state <= write_state;
end if;
elsif(count = 250000) then
count <= count + 1;
state <= idle_state;
end if;
when idle_state =>
if(count > 250000 and count < 500000) then
GPIO_0(0) <= '0';
--GPIO_0(1) <= '0';
--GPIO_0(3) <= '1';
if (count = 499999) then
count <= 101;
state <= write_state;
else
count <= count + 1;
state <= idle_state;
end if;
end if;
end case;
end if;
end if;
end process;
end arch;
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