FlyingDutch
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Hello,
I need a single pulse after pushing button (FPGA). I know how to debounce signal from button, but signal after debounce is too long (in best case i want one clock signal). So when I push button then one clock pulse be generated. I find such example of circuit that provide needed behavior - see link:
https://www.fpgakey.com/technology/...e-pulse-generator-circuit-in-fpga-development
I implemented such circuit (from figure 2 from link above) - here is implementation i VHDL. First it is D flip-flop (with async reset) - see code:
And here is this circuit - see code:
Could I ask if someone more experienced than me check if I implement this circuit properly. Of course I am going to write test bench and simulate this circuit (tomorrow).
Best Regards
I need a single pulse after pushing button (FPGA). I know how to debounce signal from button, but signal after debounce is too long (in best case i want one clock signal). So when I push button then one clock pulse be generated. I find such example of circuit that provide needed behavior - see link:
https://www.fpgakey.com/technology/...e-pulse-generator-circuit-in-fpga-development
I implemented such circuit (from figure 2 from link above) - here is implementation i VHDL. First it is D flip-flop (with async reset) - see code:
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity DFF_AsyncReset is
port(
Q : out std_logic;
QNot : out std_logic;
clk : in std_logic;
reset: in std_logic;
D :in std_logic
);
end DFF_AsyncReset;
architecture Behavioral of DFF_AsyncReset is
begin
process(clk,reset)
begin
if(reset='0') then
Q <= '0';
QNot <= '1';
elsif(rising_edge(clk)) then
Q <= D;
QNot <= (not D);
end if;
end process;
end Behavioral;And here is this circuit - see code:
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity monostable_ff is
port(
mono_pulse : out std_logic;
clk : in std_logic;
reset: in std_logic;
key : in std_logic
);
end monostable_ff;
architecture Behavioral of monostable_ff is
component DFF_AsyncReset is
port(
Q : out std_logic;
QNot : out std_logic;
clk : in std_logic;
reset: in std_logic;
D :in std_logic
);
end component;
signal Q1,Q2,Q3,Q4 : std_logic;
signal Q1N,Q2N,Q3N,Q4N : std_logic;
signal G1O : std_logic;
begin
DFF1: DFF_AsyncReset port map (
Q => Q1,
QNot => Q1N,
clk => clk,
reset => reset,
D => key
);
DFF2: DFF_AsyncReset port map (
Q => Q2,
QNot => Q2N,
clk => clk,
reset => reset,
D => Q1
);
DFF3: DFF_AsyncReset port map (
Q => Q3,
QNot => Q3N,
clk => clk,
reset => reset,
D => '1'
);
G1O <= (Q2 and Q3);
DFF4: DFF_AsyncReset port map (
Q => mono_pulse,
QNot => Q4N,
clk => clk,
reset => reset,
D => G1O
);
end Behavioral;Could I ask if someone more experienced than me check if I implement this circuit properly. Of course I am going to write test bench and simulate this circuit (tomorrow).
Best Regards
