UCC28C43 PWM IC- don't understand It's duty cycle control

[wei9321]

ucc28c43

It is current mode PWM IC
I don't understand It's duty cycle control from It's functional block diagram.
Is the duty width magnitude decided by CS and OSC ?

 

[yus]

Re: UCC28C43 PWM IC

as what I undestand w/ this type of controllers:
aside from frequency setting, it is the RTCT/oscillator(particularly the Rt) which sets the maximum duty cycle.
while the CS, as well as the COMP and FB, is the one who controls the actual duty cycle.

 

[eem2am]

UCC28C43 PWM IC

its liek voltage mode but the ramp is provided by the current through the current sense resistor....the current ramp threshold is set by the output of the error amplifier....to a maximum of 1 Volt threshold

 

[binaryninja]

Hi I am also working on a project with this IC and am having the same problem. The chip is just like the older UC3843. I tried following the charts in the datasheets but still don't have it right.

I want a max duty cycle of somewhere around 25%. Now I know there is an alternative chip in the same family that limits the duty cycle to 50% by using an internal f/f but I already have several UCC38C43's. I followed the charts and the equation (from the UC3843 datasheet) which is f= 1.72/(Rt * Ct). I am using a 470pF with 27k, it comes out to about 135kHz. Tested with a function generator and in simulation that this works. However, the duty cycle of the circuit is at max, near 98%. It kills my switching.

Can someone please explain to me how limiting the duty cycle is accomplished? If I can't do it at that frequency on the IC is there a way to do it outside of the chip on the OUTput pin? Thanks!

 

[mtwieg]

Hi I am also working on a project with this IC and am having the same problem. The chip is just like the older UC3843. I tried following the charts in the datasheets but still don't have it right.

I want a max duty cycle of somewhere around 25%. Now I know there is an alternative chip in the same family that limits the duty cycle to 50% by using an internal f/f but I already have several UCC38C43's. I followed the charts and the equation (from the UC3843 datasheet) which is f= 1.72/(Rt * Ct). I am using a 470pF with 27k, it comes out to about 135kHz. Tested with a function generator and in simulation that this works. However, the duty cycle of the circuit is at max, near 98%. It kills my switching.

Can someone please explain to me how limiting the duty cycle is accomplished? If I can't do it at that frequency on the IC is there a way to do it outside of the chip on the OUTput pin? Thanks!

The max duty cycle is set by the duty cycle of the clock signal generated internally by the oscillator. The max duty cycle of the PWM will be 1-duty cycle of the clock. The oscillator is low while the capacitor is charging CT is charging through RT. When the ramp voltage hits the max threshold, CT will be discharged linearly through a current source (linearly if the current from RT is not significant). During this time the oscillator output is high and the PWM output is disabled; this is the dead time. So if you want a low maximum duty cycle, you want a large dead time and a large CT and small RT. The issue with this is that as RT shrinks, it starts to steal significant current from the discharging current source. This will throw off the estimated frequency and dead time, and in worst case may prevent CT from discharging to the lower threshold, causing the oscillator to stop.

Getting a 25% max duty cycle may not be feasible for you with that chip. If possible I'd try to get the part with the internal ff.