Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Re: typical application of "-add" option of create
Modifying the clock tree latency can have quite a big impact on the timing violations. If you 'd like to analyze your design assuming a different clock latency, it is possible to add an delay to the clock-source pin.