Beside my previous post
If you allowed me, I want to ask some questions about the error amplifier:
My LDO is preceded by a rectifier, the rectifier generates 2v DC from a 13.56meg AC signal, say with ripples 0.1v, My guess that these ripples would be also at 13.56meg and its harmonics, hence My LDO should have a very large PSRR BW, let say 50Meg, am I right ? If so, I guess the DC gain should be minimized, Let say 20-30db ? am I right ?
Another thing, The max current the LDO should supply is very small, typically 1-2mA, So the pass element area is also small, I simulated an ideal circuit and found that its gate capacitance will be less than 1p !! Is this reasonable ? If so, I guess 60deg for the phase margin is fine
Also, ICMR should be something around 1.2v (my BG reference), I guess 1-1.4 is fair enough
what about output swing?
I am still confused about SR and not sure how to relate it to the LDO specs, I guess this parameter is important when Load current steps from max (1mA) to min (0) and related to the transient specs; overshoot and settling time, am I right ?
I also made a Matlab model for the loop, but still not sure what is next to do ? should I vary every stage gain and BW and see the effect on PSRR or stability ?
I think this matlab model might help only in OTA design (not related to the pass element and feedback) choosing optimum value for gain, BW, SR, etc
am I right ?
Thanks sir