Two-stage amplifier in CMOS design

[Castanheira_ua]

Good afternoon. I am attending a course in electronics in Portugal, and I'm having some doubts in the design of a two-stage amplifier in CMOS technology.
I cannot get a sufficiently high gain, about 100000V / V.
And the unity gain frequency should be about 1MHz.

The input stage is a differential pair with PMOS and the output stage is a common source.

I would appreciate some kind of help.
I enclose pictures of my circuit and the corresponding Bode diagram.

Thank you for your help and sorry for my English.

---------- Post added at 16:39 ---------- Previous post was at 16:39 ----------

Sorry, but i must have two submitted posts in order to post links.

Bode Diagram:
h**p://img46.imageshack.us/i/boder.jpg

Amplifier Circuit:
h**p://img407.imageshack.us/i/amplificador.jpg

 

[steadymind]

I would suggest you look into

cmos analog design book by phillip allen ( 2nd edition). it has a chapter which discusses how to design two stage amplifier and the trade offs.

do not test your amplifier in open loop, have a closed loop system which a big resistor(1GOhms) between ur output and negative input. this will help u calculate the input referred error, increase the gain by increasing the length of the nmos load in first stage. from bode plot we can see the second pole is affecting your Phase and needs better compensation.

 

[ayo_oc]

Try cascoding the load. Then to get more gain, you can boost the transconductance of the loads also to increase the output resistance and thus the gain. Usually the best way is to split the gain about equally btw the 2 stages. To increase the unity gain frequency, you can add a resistor in series with the compensating capacitor (feedback). But u need to do a quick hand analysis so you know what parameters affects your gain and Unity gain frequency. Circuit Design is like a game of Lego....you have to put things together step by step. Goodluck!

 

[tokwatbaboy]

Hi All,
I am trying to design a two-stage op-amp using 0.35um technology. I am currently lost on how to start my design. Our professor gave us a circuit which is 2 pmos diff pair as the input and based from that we start our design. Now my problem is how to estimate the transistor sizes. I am trying to check the voltages (vgs, vds) on all transistors but with no success. I tried to tie both p and n inputs to ground and check if my transistors are in saturation region and found out that my nmos current mirror and pmos current source are on saturation while my two pmos inputs are at linear. is that the correct state of my transistors?

Can you please give also some techniques on how to start my design. Specs requires 80db Gain/CMRR/PSRR, 100MHz Unity Gain BW, 3V Vdd and 0V Vss.
Thank you!

 

[jimito13]

Try this link :

**broken link removed**

It's a good tutorial to study before you start the design and you will see how each parameter affects your performance.

...is that the correct state of my transistors?

No,all transistors should work in saturation region.You should find a proper common mode input voltage that ensures all transistors are in sat while
reaching your specs on the other hand.

 

[tokwatbaboy]

thanks! i will check and review the file. Also, one question is, do i have to force gnd to inputs during DC computation?

 

[jimito13]

I don't understand...if you mean to connect the small-signal to ground for DC analysis,the answer is yes.
As fas as DC common mode input level the answer is apparently no!

 

[tokwatbaboy]

what i want to do is to estimate the vds/vgs of transistors m3 and m4 (nmos current mirror), vds/vgs of transistors M1 and M2 (pmos diff pair) and vds/vgs of M5 (pmos current source). I want to see if 3.3 vdd supply is enough to support my whole circuit.

 

[jimito13]

what i want to do is to estimate the vds/vgs of transistors m3 and m4 (nmos current mirror), vds/vgs of transistors M1 and M2 (pmos diff pair) and vds/vgs of M5 (pmos current source).

Ok,this is up to the designer's choises according to what he wants to achieve with his amplifying stage.

I want to see if 3.3 vdd supply is enough to support my whole circuit.

Read the manual of this process and see what is the maximum Vdd that can be used for this type of transistor you use.This is your Vdd for the opamp.

 

[simulationcircuits]

Hi all,
i want to design a bipolar supply (5) with cmos having minimum components,the input frequency is 100kHz and the op-amp must have an open loop gain of of at least 100.