Fully differential amplifier design

[Punchudo]

Hey,
We've given a task to design a fully differential amplifier using cadence virtuoso.
We are allowed to use only a single DC supply VDD, and given the following required specs:

1. You must design this amp including a CMFB, all bias circuits and bias reference circuits. You have complete freedom in choosing the topology.
2. Specs:

• VDD = 2V
• Closed Loop Gain = 2
• Dynamic range at output >80 dB
• Settling Error < 0.5 mV
• Settling Time, Ts < 50 ns
• Load capacitance = 10 pF
• Phase Margin > 60 Degrees
• Power dissipation - Keep as low as possible

What is the best approach to start the task? Which fully differential configure is best suited for these requirements? How can I know if a 2nd stage is needed?

Thanks.

 

[BradtheRad]

differential amplifier

The topology most commonly associated with differential detection is long-tail pair. It resembles two class A transistor amplifiers side-by-side sharing a percentage of one power supply. If either transistor takes more mA then it subtracts from the other.
If either transistor reduces its share of mA then the other can take more.

It can run on a single-polarity DC supply but you must adjust bias carefully to each transistor. You might manage to obtain gain of 2 and you must adjust voltage ranges carefully to operate inside your power supply of only 2V.

 

[Punchudo]

The topology most commonly associated with differential detection is long-tail pair. It resembles two class A transistor amplifiers side-by-side sharing a percentage of one power supply. If either transistor takes more mA then it subtracts from the other.
If either transistor reduces its share of mA then the other can take more.

It can run on a single-polarity DC supply but you must adjust bias carefully to each transistor. You might manage to obtain gain of 2 and you must adjust voltage ranges carefully to operate inside your power supply of only 2V.

By long-tail, do you mean these schematics?

I am thinking connection active load PMOS, and biasing them for my desired voltage.
Also, connecting the output (Vout+/Vout-) to a current sink below M1,M2
something like this :

But how can I be sure that I could even get the specs I need? Should I just try achieving that using this schematic and hope for the best?

Thank you!

 

[dick_freebird]

Your first best bet would be to go search out IEEE papers
(solid state circuits) on low voltage CMOS op amps in the
1.8V supply range. These should at least give you a set of
"go and try" options, topology- and results-wise.

 

[BradtheRad]

By long-tail, do you mean these schematics?

Yes -Those are examples which illustrate basics. It all depends whether the exercise is intended to further your knowledge in regard to using op amps (fully differential type) or in regard to building and customizing a long-tail pair. (Generally the op amp has a differential detector as its first stage. It may be P-devices or N-devices. The tail resistor/transistor is usually at the emitters.)

Since you're simulating it's a good idea to build both. You were given numerous specs to obey. Watch if you discover a point where your given specs imply you should experiment with one project yet hamper you from continuing with the other project.

 

[nitishn5]

Hey,
We've given a task to design a fully differential amplifier using cadence virtuoso.
We are allowed to use only a single DC supply VDD, and given the following required specs:

1. You must design this amp including a CMFB, all bias circuits and bias reference circuits. You have complete freedom in choosing the topology.
2. Specs:

• VDD = 2V
• Closed Loop Gain = 2
• Dynamic range at output >80 dB
• Settling Error < 0.5 mV
• Settling Time, Ts < 50 ns
• Load capacitance = 10 pF
• Phase Margin > 60 Degrees
• Power dissipation - Keep as low as possible

What is the best approach to start the task? Which fully differential configure is best suited for these requirements? How can I know if a 2nd stage is needed?

Thanks.

1. Back calculate the Open Loop Gain and Bandwidth Specification.
2. Also check the Input and Output Common mode Range. (Rail to Rail input/output or anything else.

From 2 you can decide whether you need NMOS input or PMOS input or both(rail to rail)
From 2 you can also figure out whether you have enough headroom at 2V supply to cover the high gain single stages(like Telescopic or Folded Cascode)

From 1 figure out how much gain is needed and along with the above you should be able to choose between the following

1. Simple 5 Transistor OTA (The one whose pic you have attached 1st) - Lowest Gain ~ 40dB
2. Single Stage Telescopic - Very High Gain ~60dB, limited Output Range
3. Single Stage Folded Cascode - Very High Gain ~60dB, slightly better output range.
4. Dual Stage with 1st stage simple 5 transistor OTA and 2nd Stage as Common Source - Very High Gain, Good output Range
5. Dual Stage with 1st stage Telescopic OTA and 2nd Stage as Common Source - Very High Gain, Good output Range
6. Dual Stage with 1st stage Folded Cascode OTA and 2nd Stage as Common Source -High Gain, Good output Range
7. There are more options of course which you can look up in case you dont like any of the above .

You can definitely get better gains from the above than what I have mentioned. But this will be at the cost of something(Power/Range).

I would suggest Option 4. Don't overcomplicate. There are plenty of resources on basic 2 stage opamp design.
Use some Basic compensation like miller to get the stability you want.
Use the method in books like Razavi to figure out the gm, Tail current, etc needed to meet your specifications.

Use an ideal CMFB till you close the opamp design. Then work on the CMFB and other biasing.

 

[Punchudo]

1. Back calculate the Open Loop Gain and Bandwidth Specification.

Thank you for suggesting Razavi, it has been very helpful
However, maybe it's a stupid question, but i can't seem to solve this problem :

Every amplifier I've seen using NMOS differential input. We are allowed to use only a single DC supply, VDD = 2V.
How can I bias the NMOS without VSS? If the gate has to be 0V, given ground is the lowest voltage, VGS will always be negative.
Am I missing something? How can a circuit without VSS operate without biasing the input?

And thank you all for your replies

 

[nitishn5]

I am not sure what you mean "without VSS" I am guessing a negative VSS.

But any way, as you would have been taught, the critical specification for this would be Input Common Mode Range.

What is the range of inputs your OPAMP can expect to work with? Is it Rail to Rail (0 to VDD) or more limited such as 1V to 2V
If your amplifier has only NMOS input pair, then it can't obviously work from 0V input. It needs to have some minimum Input voltage so that the devices are operational.
On the other side we can use the PMOS input pair for say 0V to a maximum input voltage.
If you want to amplifier to work in the full VSS to VDD range, then you need BOTH PMOS and NMOS differential input pairs. (Search for Rail to Rail input stages)

Assuming this to be some class project, build with just the NMOS input pair and have a limited specification for your Input range.

But make sure you understand the above so that you have an answer during job interviews.

 

[Punchudo]

I am not sure what you mean "without VSS" I am guessing a negative VSS.

Thank you nitishn5, I've found your replies very useful.

By "without VSS", meaning that VSS is ground.
The project specs says that only one DC source can be used, and it is VDD. Which got me confused on how to bias the input (we can't use DC voltage at the gate).
I've figured with the help with some classmates that we should bias using transistors :

Which should be obvious from previous courses, but somehow slipped my mind.
Using your guidance and help to deepen my understanding of fully differential amplifying, I can now start my design.

Many thanks!