vivek_p
Advanced Member level 4
In my design I want to use two (2) identical memories. I have written a code for the memory in Verilog HDL.
Say my module is "mem.v"
// Instantiation
mem m1 (port lists);
mem m2(port lists);
I have instantiated the memories as above. I want to initialize the two memories with different values. How can I do it without creating two copies of the memory, I mean say "mem1.v" and "mem2.v".........and initialise it independently.
Please help me.....Urgent
Say my module is "mem.v"
// Instantiation
mem m1 (port lists);
mem m2(port lists);
I have instantiated the memories as above. I want to initialize the two memories with different values. How can I do it without creating two copies of the memory, I mean say "mem1.v" and "mem2.v".........and initialise it independently.
Please help me.....Urgent