Two memories with different values in Verilog HDL

[vivek_p]

In my design I want to use two (2) identical memories. I have written a code for the memory in Verilog HDL.

Say my module is "mem.v"

// Instantiation
mem m1 (port lists);
mem m2(port lists);

I have instantiated the memories as above. I want to initialize the two memories with different values. How can I do it without creating two copies of the memory, I mean say "mem1.v" and "mem2.v".........and initialise it independently.

Please help me.....Urgent

 

[amraldo]

Re: Memory - help required

What about initializing them by a code u run at the start of the simulation?
--
Amr Ali

 

[vivek_p]

Re: Memory - help required

Can u please explain it in detail with an example

 

[amraldo]

Re: Memory - help required

I did not code in verilog long time ago, I cant show an example. I will look for one.
My idea is to write a function the loads data into each memory at reset.
--
Amr Ali

 

[vivek_p]

Re: Memory - help required

But can a function be synthesised using Xilinx or Synopsys

 

[amraldo]

Re: Memory - help required

A function and procedure can be synthesized but why do you need to initialize a memory at run time?!! That's usually the task of the boot loader.
--
Amr Ali

 

[vivek_p]

Re: Memory - help required

Can anyone post a sample code???? Please

 

[skyfaye]

Re: Memory - help required

This is how I would do it. Since you wrote mem.v yourself, you can add the init routine inside there as well.

For example:

// mem.v
module mem;
reg [7:0] mem_array[99:0]; // memory array

task init;
input [200*8-1:0] data_file; // 200 max chars for data file name

$readmemb (data_file, mem_array);
endtask
endmodule;

// top.v
module top;
mem m1 (port lists);
mem m2(port lists);

initial begin
m1.init("m1_data_file.txt"); // init memory 1 with data file
m2.init("m2_data_file.txt"); // init memory 2 with data file
end
endmodule;


Hope this helps.

- Hung

 

[vivek_p]

Re: Memory - help required

Is the above code synthesisable in Xilinx and Synopsys