Two dimensional input port in verilog, compilation error with unpack_array macro

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hulk789

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Referring to previous thread https://www.edaboard.com/threads/80929/

`UNPACK_ARRAY(4,16,in,pack_4_16_in)
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ncvlog: *E,EXPEND (pack.v,12|34): Expecting the keyword 'end' [12.1.3(IEEE 2001)].
(`define macro: UNPACK_ARRAY [pack.v line 3], file: pack.v line 12)
`UNPACK_ARRAY(4,16,in,pack_4_16_in)
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ncvlog: *E,UMGENE (pack.v,12|34): An 'endgenerate' is expected [12.1.3(IEEE 2001)].
(`define macro: UNPACK_ARRAY [pack.v line 3], file: pack.v line 12)
`UNPACK_ARRAY(4,16,in,pack_4_16_in)
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ncvlog: *E,EXPENM (pack.v,12|34): expecting the keyword 'endmodule' [12.1(IEEE)].
(`define macro: UNPACK_ARRAY [pack.v line 3], file: pack.v line 12)
endmodule // example
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ncvlog: *E,UMGENE (pack.v,20|8): An 'endgenerate' is expected [12.1.3(IEEE 2001)].
module worklib.example:v
errors: 4, warnings: 0
the following errors are obtained while compiling your code
 
Last edited by a moderator:

Looks like an incorrect copy and past problem.

You should better append the actual code you have compiled.
 

Code Verilog - [expand]
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`define PACK_ARRAY(PK_WIDTH,PK_LEN,PK_SRC,PK_DEST);    genvar pk_idx; generate for (pk_idx=0; pk_idx<(PK_LEN); pk_idx=pk_idx+1) begin; assign PK_DEST[((PK_WIDTH)*pk_idx+((PK_WIDTH)-1)):((PK_WIDTH)*pk_idx)] = PK_SRC[pk_idx][((PK_WIDTH)-1):0]; end; endgenerate
 
`define UNPACK_ARRAY(PK_WIDTH,PK_LEN,PK_DEST,PK_SRC); genvar unpk_idx; generate for (unpk_idx=0; unpk_idx<(PK_LEN); unpk_idx=unpk_idx+1) begin; assign PK_DEST[unpk_idx][((PK_WIDTH)-1):0] = PK_SRC[((PK_WIDTH)*unpk_idx+(PK_WIDTH-1)):((PK_WIDTH)*unpk_idx)]; end; endgenerate
 
 
module example (
    input  [63:0] pack_4_16_in,
    output [31:0] pack_16_2_out
    );
 
wire [3:0] in [0:15];
`UNPACK_ARRAY(4,16,in,pack_4_16_in)
 
wire [15:0] out [0:1];
`PACK_ARRAY(16,2,in,pack_16_2_out)
 
 
// useful code goes here
 
endmodule // example
 
Last edited by a moderator:

I see several conflicts with usual Verilog syntax. Don't know in which context the original code had been used.

According to my (limited) Verilog knowledge, the macros should look like below:

Code Verilog - [expand]
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`define PACK_ARRAY(PK_WIDTH,PK_LEN,PK_SRC,PK_DEST)    genvar pk_idx; generate for (pk_idx=0; pk_idx<(PK_LEN); pk_idx=pk_idx+1) begin:b1 assign PK_DEST[((PK_WIDTH)*pk_idx+((PK_WIDTH)-1)):((PK_WIDTH)*pk_idx)] = PK_SRC[pk_idx][((PK_WIDTH)-1):0]; end endgenerate
 
`define UNPACK_ARRAY(PK_WIDTH,PK_LEN,PK_DEST,PK_SRC) genvar unpk_idx; generate for (unpk_idx=0; unpk_idx<(PK_LEN); unpk_idx=unpk_idx+1) begin:b2 assign PK_DEST[unpk_idx][((PK_WIDTH)-1):0] = PK_SRC[((PK_WIDTH)*unpk_idx+(PK_WIDTH-1)):((PK_WIDTH)*unpk_idx)]; end endgenerate
 

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