Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

tsmc epi layer option, which epi is better to prevent latchu

Status
Not open for further replies.

lionking819

Newbie level 3
Joined
Aug 8, 2009
Messages
4
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Location
san jose
Activity points
1,305
epi resistance

I was told by TSMC person that they have two epi layer option to select
1. normal epi (resistance 6-8Ohm)
2. special epi (no doping, really high resistance and thinner than normal epi)
does anybody use the special epi layer before?
to prevent latchup, which one is better?

thanks
 

erikl

Super Moderator
Staff member
Joined
Sep 9, 2008
Messages
8,112
Helped
2,689
Reputation
5,358
Reaction score
2,289
Trophy points
1,393
Location
Germany
Activity points
44,153
Re: tsmc epi layer option

lionking819 said:
... to prevent latchup, which one is better?
I'm not absolutely sure, but from physical reason the lower-resistance epi should be better. The higher-resistance epi layer is for HV applications ( > 5V ).
 

jian1712

Newbie level 1
Joined
Jan 21, 2009
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,284
tsmc epi layer option

lower resistance epi is better to prevent latch-up
 

deepak242003

Full Member level 5
Joined
Dec 24, 2008
Messages
310
Helped
43
Reputation
86
Reaction score
16
Trophy points
1,298
Location
Banglore
Activity points
2,818
tsmc epi layer option

erik is correct.. because lower the resistance more will be current required to trigger the parasitic SCR......
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top