There are various breakdown mechanism and we can distinguish:
1. Hard breakdown (permanent damage)
2. Soft breakdown
Also, transistor is complicated device so, various types of breakdown can occurs:
A. Gate Insulator breakdown
B. Junction breakdown
C. Channel breakdown
Soft breakdown is like lightning, due to high electric field acting on gate Insulator, charge start to leak through the Insulator defects and finały create a way to channel. We see it as increased leakage current in gate with glitch, after which current back to "standard" value.
The numbers can be different for all above types.
Usually junctions can resist 6-10 V, gate dielectric has strength in order of 0.5V/nm (so if you gate thickness is 5nm it can resist up to 2.5V).
High electric field in Channel (Vds/L) generates Towsend ionisation in Channel and burns transistor. This number depends on channel length, and might be in order of tens or even hundred V/um.
The other question is what voltage/electric field is safe for transistor to ensure high yield and reliable work for long time.
Typical limits considered by foundries is nominal VDD+10%. It means that 2.08V is max value of Vgs and Vgd for which you fet is ensured to work fine.
For Vds the value is length dependant and usually for Vdb and Vsb, numbers are much higher than supply (it is a pn junction so is quite reliable).
If you want be safe, follow 1.1*VDD rule and check SOA during transient.