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Trying to decide the least-component technique to implement these circuits

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rush3k

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Latched.PNG
Latched2.PNG

Any ideas or suggestions to implement this in digital logic?
 
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mister_rf

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Try this way: :grin:

If it’s necessary to have both situations we can change, see the diagram.
 

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rush3k

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Mister_rf thanks for your reply. Your circuit with the DFF assumes we'll always about ~4 pulses? I had failed to point out that we have an unknown number of pulses ...
I'm interested in understanding how to implement for both. I have been playing with a technique with an SR-latch ... latching on the rising edge and then switching to a "high state" so the output stays high ..., but that's still under investigation. Any further ideas are welcome ... thanks!
 

alexan_e

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This is why you should explain in detail what you want.
In this case there was only a sketch with four pulses and a second pulse with duration of four clocks and you have asked how to implement it, naturally you got an answer for exactly that.
So take your time when you ask questions and write what you want, no one can guess what your actual need.

Best regards
Alex
 

rush3k

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This is why you should explain in detail what you want.
In this case there was only a sketch with four pulses and a second pulse with duration of four clocks and you have asked how to implement it, naturally you got an answer for exactly that.
So take your time when you ask questions and write what you want, no one can guess what your actual need.

Best regards
Alex

Understood. Thank you.
 

mister_rf

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Sometimes all details are important. :grin:
See the attached examples.
 

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  • timing2.GIF
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rush3k

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Sometimes all details are important. :grin:

Yes, I have drawn a better picture and description. What I was trying to express is that the width of the output pulse should stretch from the first rising edge to the last falling edge as I have shown on the picture. I'm sorry for not presenting this in a better way :/

BetterDescription.png
 

mister_rf

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You can’t put in practice a circuit to follow this description. If we use an unknown number of pulses, how come you can predict when it's time the signal to stop?
 
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FvM

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A feasible cicrcuit with a similar behaviour is a retrigerable pulse stretching monoflop. But of course, the output pulse must exceed the last falling input edge by some time amount. I hope, the explanation by mister_rf has been clear in this regard.

 

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