Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

[SOLVED] How to implement mosfet with large width

Status
Not open for further replies.

nithinp

Junior Member level 2
Joined
Dec 26, 2023
Messages
23
Helped
0
Reputation
0
Reaction score
1
Trophy points
3
Location
India
Activity points
146
I'm doing a project on LDO , I was calculating the W/L ratio of pass transistor(PMOS) which turned out to be approx 8600, so I put W=4300u, L=0.5u. I'll absolutely get an error bcs the width exceeds the max width given by the foundry, How can I overcome this problem
 

No I calculated the W/L ratio correctly , I got W/L of pass transistor as 8600, but problem is I cannot use a single mosfet with such a large W, so how can I implement a mosfet with such a high W, One guy suggested to use multiplier option with m=100, the width becomes W/100. I have no idea how to implement such a large transistor or multipliers
 

Stripes. Lots of stripes. Pay attention to electromigration and
layout, current flow. Make finger width no wider that what a
drain finger metal width over topography can support for
peak and average max current spec, unless you are sure
you can take it out vertically to fatter Met2 (and use as many
vias as you can fit, double row, enlarge Met1 if need be.
 

Along with ultra-low RdsOn and Vgs is high Cout, Cin, Cdg and stability concerns with low ESR C load ranges.
I wonder what the limitations are for partial discharge in the gap at max V or fabrication challenges?
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top