Tristate inverter buffer not found

[kannanunni]

Error : Unable to map design without a tristate buffer or inverter. [MAP-1] [synthesize]
: The design is 'minsoc_top'.
: Check the libraries for necessary tristate cell. The cell could be marked unusable.

so
how to find tristate inverter from timing lib???

i'm using FUJITSU CS202SN slow process 1.25v lib..

 

[artmalik]

you should see the Error....there is a need for inverter....tristate inverters are not good for STA....so they should be avoided.

 

[kannanunni]

so how i procced?
i mean how to rectify this error?

 

[artmalik]

I meant to say that setup is not okay...because even if the library doesn't have a tri-state inverter it got to have inverters....please check with setup so that it is able to reading in the library correctly and has all the cells in it that you need

 

[kannanunni]

i'm new in this synthesis area , and i didn't know how to check library cells for usability ..
could you please tell me in detail..??

i think the lbrary is loading perfectly without any warning..
one more question too..
if i change multibit mapping(multibit_preserve_inferred_instances) to false will solve the problem. right?

 

[kannanunni]

I meant to say that setup is not okay...because even if the library doesn't have a tri-state inverter it got to have inverters....please check with setup so that it is able to reading in the library correctly and has all the cells in it that you need

my initial tool configuration file is like this..


set_attr source_verbose 1 /
#proc log_source_command { command filename line_number } { puts "<CMD> $command" }

# =====================================================================
# * Define the Library
# =====================================================================
set_attr lib_search_path "/odc/nest2/tools/FJ/x86_64/RDF_110506/RDF/lib/rf-source/CS202/CS202SN \
/odc/nest2/tools/FJ/x86_64/RDF_110506/RDF/lib/rf-source/CS202/common"
set_attr library "cs202sn_uc_core_s_p125_10v.lib \
cs202sn_uc_dscan_s_p125_10v.lib \
cs202sn_uc_aob_s_p125_10v.lib \
cs202sn_uc_eco_s_p125_10v.lib \
cs202sn_uc_nscan_s_p125_10v.lib \
cs202sn_uc_scan_s_p125_10v.lib \
cs202_io_s_p125_m_11v_30v.lib"

# =====================================================================
# * Define the Diagnostic Variables
# =====================================================================
set iopt_stats 1
set map_timing 1
set global_map_report 1
set map_fancy_names 1
set report_unfolding 1
set cost_grp_details_in_iopt 1

# =====================================================================
# * Define Tool Setup and Compatibility
# =====================================================================
set_attribute super_thread_servers {localhost localhost localhost localhost localhost localhost localhost localhost}
set_attr information_level 9 /
set_attr hdl_max_loop_limit 1024
set_attr hdl_reg_naming_style_vector %s_reg_%d_ /
set_attr bit_blasted_port_style %s\[%d\] /
#set_attr gen_module_prefix RC_DP_${MODULE}_ /
set_attr inst_prefix {U}

set_attr endpoint_slack_opto true /
set_attr hdl_ff_keep_feedback false /
set_attr hdl_array_naming_style %s_%d_ /
set_attr hdl_undriven_output_port_value 0 /
set_attr hdl_unconnected_input_port_value 0 /
set_attr hdl_undriven_signal_value 0 /
set_attr bit_blast_constants true /
set_att optimize_constant_0_flops true /
set_att optimize_constant_1_flops true /
set_att optimize_constant_latch true /
set_attr delete_unloaded_seqs true /
set_attr drc_first true /



from this , what you meant by "Setup is not okey" ??

please reply..