Tri-mode gates issue after synthesizing RTL code

[flyankh]

Tri-mode issue

Hi ,all
I used tri-mode gates in my design,but after I synthesis the RTL code ,it give me a netlist which contain a net type "tri",and there are some instances named "tran",in fact there didn't have a standard-cell with same name.
For example:
There have one "tri" net named "data" the 'tran" instance looks like this
tran(data_wire data)
In fact "data_wire" and "date" is the same net.
Have anybody meet this trouble?Give me some advice please.

Best regards

flyankh

 

[stormwolf]

Tri-mode issue

I remember at dc have "change_name" command to do this, you should read this command and the naming rule of dc.