udintbr
Newbie level 4
I have a simple double ended output diff pair
- vdd = 2.5V, vss = 0
- small gain (Av = 2)
- input transistors (m1 & m2)= nmos
- load transistors (m3 & m4) = diode-connected pmos
- min input common mode, vic(min) = 0.8V
- nmos (M5) tail current = 100uA
operating points ok, ac plot ok (almost 0 db). having some problems with transient analysis
I set the following config to the ins & outs:
dc=1V + 1mV sine wave to 1st input
dc=1V + 1mV sine wave (180 out of phase) to 2nd input
CL = 2pF to both output ends
What i got is
- input ok (1mV sine wave at dc level =1V)
- output 2mV sine wave but at dc level 1.455V
I got a few questions
1) did i set the testbench correctly? offset is large 0.455V? if I omit the dc=1V, all transistors will be in cut-off (except m5). what did i do wrong? since the gain is almost unity, shouldn't the dc offset be very small?
2) is it possible to set vic(min) to be 0V? i did that but then i got vds(sat) of M5 to be -ve.
3) if i set vic(min) close to 0V, I will get vds5(sat) -ve value in my calculation. [Vic(min) = Vds5(sat) + Vgs1]. any other to do this? is there any rule of thumb on the appropriate icmr for a given vdd to vss range (in this case, 0 to 2.5V vdd)?
4) if i want to use pmos as the input transistors, how to determine W/L of M5. I used Vic(min) = Vds5(sat) - Vtp. I couldn't get M5 to be in saturation no matter what vic(min) I used.
sorry for the long text. eager to learn. may have more questions.
TQ
- vdd = 2.5V, vss = 0
- small gain (Av = 2)
- input transistors (m1 & m2)= nmos
- load transistors (m3 & m4) = diode-connected pmos
- min input common mode, vic(min) = 0.8V
- nmos (M5) tail current = 100uA
operating points ok, ac plot ok (almost 0 db). having some problems with transient analysis
I set the following config to the ins & outs:
dc=1V + 1mV sine wave to 1st input
dc=1V + 1mV sine wave (180 out of phase) to 2nd input
CL = 2pF to both output ends
What i got is
- input ok (1mV sine wave at dc level =1V)
- output 2mV sine wave but at dc level 1.455V
I got a few questions
1) did i set the testbench correctly? offset is large 0.455V? if I omit the dc=1V, all transistors will be in cut-off (except m5). what did i do wrong? since the gain is almost unity, shouldn't the dc offset be very small?
2) is it possible to set vic(min) to be 0V? i did that but then i got vds(sat) of M5 to be -ve.
3) if i set vic(min) close to 0V, I will get vds5(sat) -ve value in my calculation. [Vic(min) = Vds5(sat) + Vgs1]. any other to do this? is there any rule of thumb on the appropriate icmr for a given vdd to vss range (in this case, 0 to 2.5V vdd)?
4) if i want to use pmos as the input transistors, how to determine W/L of M5. I used Vic(min) = Vds5(sat) - Vtp. I couldn't get M5 to be in saturation no matter what vic(min) I used.
sorry for the long text. eager to learn. may have more questions.
TQ