Training for Gate Level Simulation

I'm lacking experience in Gate Level Simulation so I want to practice more or gain more experience on solving issues on this level. The problem is, I want to do this at home, not in my office, so I need a software tool that can run GLS. Cadence and Synopsys need a license and that is very expensive. I can't pay that much just to do some practices... So do you know any free tool which I can use?.. Aside from tool, I think I need a library too for the gates. Where can I find these?..

I tried the EDA Playground but I don't think the synthesis tool there actually converts the RTL code to a gate-level netlist.. I don't know. Maybe I'm doing it wrong. If you have any experience on using EDA Playground, you can give me advice on how to synthesize and run GLS there.

Synthesis and simulation are completely different tasks to which you apply completely different tools. You can try modelsim for simulation, there is a free student version. For synthesis you most likely need cadence/synopsys.

iverilog is probably one of the only simulation tools that is "free" that you could likely run a huge gate level simulation on. Free student version of Modelsim etc are lobotomized and will run very slow. Based on claims of the author there have been ASICs taped out using that simulator. You usually get a gate level simulation library from the ASIC vendor for their process. Have no clue if there are any truly open source gate level simulation libraries that you can download.

Don't make any requests for proprietary libraries as that is a violation of forum rules.

ads-ee said:

Have no clue if there are any truly open source gate level simulation libraries that you can download. .

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freePDK 15nm comes with a library (http://www.nangate.com/?page_id=2328). synopsys (SAED) offers one too. there are more, probably outdated by now.

Reading the page on freePDK seems to indicate it's not finished and the following quote seems to indicate it does not have simulation libraries at this time.

Available Library Views

The NanGate 15nm Open Cell Library will eventually contain the following views:

• Liberty (.lib) formatted libraries with CCS Timing, ECSM Timing and NLDM/NLPM data (multiple corners)
• Spice (pre and post parasitic extracted netlists)
• Simulation libraries in Verilog
• Geometric library in Library Exchange Format (LEF)
• Cell layouts in GDSII
• Library databook in HTML format
• OpenAccess database containing layouts and netlists

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ads-ee said:

Reading the page on freePDK seems to indicate it's not finished and the following quote seems to indicate it does not have simulation libraries at this time.

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to the best of my knowledge, it is finished.

ThisIsNotSam said:

to the best of my knowledge, it is finished.

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That's great! I'll try that and also the free student version of Model sim.
I'm also looking into buying an FPGA. I'm not sure if they will provide a library that accurately models the gates of their FPGA..

I'm lacking experience in Gate Level Simulation so I want to practice more or gain more experience on solving issues on this level. The problem is, I want to do this at home, not in my office, so I need a software tool that can run GLS. Cadence and Synopsys need a license and that is very expensive. I can't pay that much just to do some practices... So do you know any free tool which I can use?.. Aside from tool, I think I need a library too for the gates. Where can I find these?

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Putting it simply, you cannot gain skills related to ASIC development for free sitting at home. Move to FPGA and get a free IDE. You can gain knowledge starting from simulation, synthesis, timing analysis, etc.

ReubenMijares said:

That's great! I'll try that and also the free student version of Model sim.
I'm also looking into buying an FPGA. I'm not sure if they will provide a library that accurately models the gates of their FPGA..

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Definitely no. FPGA and ASIC, in this regard, are completely different monsters.

I'm interesting in this: **broken link removed**
Here is the thread that YOSYS author talk about his tool: http://www.eevblog.com/forum/microcontrollers/open-source-software-for-verilog-synthesis/

Just in case it matches with your need.