train ticket machine help needed!

[sicazoR]

HI there,

I'm designing a ticketing machine. The distance and the money are introduce by the user on a FPGA board. I have 4 states, s0 when I initialize the data, s1 when i read the distance and calculate the price for the ticket, s2 when i read the money user introduce and s3 when i compare the price with the money user introduced and give the ticket, the rest etc.

I have a problem in the state 2 of the machine. User introduces the money (1 euro = "01", 5 euro = "10" and 10 euro = "11") and when he push the clock button the signal SUM_INTRODUCED and TOTAL_SUM increases with that value as long as another input signal BTN1 is '0'. The problem is that after introducing 1 euro, if you introduce 1 euro again my signals don't change there values. But if you introduce 10 euro it change and work. Any help?

The code looks like this:

signal INTRODUCED_SUM			: unsigned (5 downto 0):="000000";
signal TOTAL_SUM				: unsigned (5 downto 0):="000000";
....
type state_type is (s0,s1,s2,s3);  --type of state machine.
signal current_s,next_s: state_type;

begin
	process (CLK,RESET)
	begin
		if (RESET = '1') then
			current_s <= s0;  
		elsif (RISING_EDGE(CLK)) then
			current_s <= next_s;   
		end if;
	end process;

prelucrare: process(current_s,BTN1)
begin
case current_s is ...
			when s2 =>
						if (BTN1 = '1') then
							next_s <= s3;
						elsif (BTN1 = '0') then
							if (SEL = "01") then
								INTRODUCED_SUM 	<= INTRODUCED_SUM + 1;
								1euro_COIN 		<= 1euro_COIN + 1;
								TOTAL_SUM 	<= 	TOTAL_SUM +1;
								
								elsif (SEL = "10") then
								INTRODUCED_SUM 	<= INTRODUCED_SUM + 5;
								5euro_COIN 		<= 5euro_COIN + 1;
								TOTAL_SUM 	<= 	TOTAL_SUM +5;
									
									elsif (SEL = "11") then
								INTRODUCED_SUM 	<= INTRODUCED_SUM + 10;
								10euro_COIN 		<= 10euro_COIN + 1;
								TOTAL_SUM 	<= 	TOTAL_SUM +10;
							end if;
							next_s <= s2;
						end if;

 

[TrickyDicky]

you are missing introduced_sum, 1euro_coin and total sum from the 2nd process sensitivity lsit. but, you will have a problem with this as they form combinatorial loops - you cannot put counters in an asynchronous process. They must be in a separate synchronous process.

 

[sicazoR]

Ok, i get it; but if I separate them like this, doesn't work at all. how should i do it?

process(current_s,BTN1)
begin
case current_s is ...
			when s2 =>
						if (BTN1 = '1') then
							next_s <= s3;
						elsif (BTN1 = '0') then
                                                        next_s <= s2;
                                                end if;
...
end process;

money:process(INTRODUCED_SUM,TOTAL_SUM,1euro_COIN,5euro_COIN,10euro_COIN)
begin
                                  if(BTN1 = '0')
							if (SEL = "01") then
								INTRODUCED_SUM 	<= INTRODUCED_SUM + 1;
								1euro_COIN 		<= 1euro_COIN + 1;
								TOTAL_SUM 	<= 	TOTAL_SUM +1;
								
								elsif (SEL = "10") then
								INTRODUCED_SUM 	<= INTRODUCED_SUM + 5;
								5euro_COIN 		<= 5euro_COIN + 1;
								TOTAL_SUM 	<= 	TOTAL_SUM +5;
									
									elsif (SEL = "11") then
								INTRODUCED_SUM 	<= INTRODUCED_SUM + 10;
								10euro_COIN 		<= 10euro_COIN + 1;
								TOTAL_SUM 	<= 	TOTAL_SUM +10;
							end if;
							next_s <= s2;
						end if;
                                     end if;
end process;

 

[TrickyDicky]

like I said - your 2nd process is asynchronous - and you cannot use counters in asynchronous processes. You need to put the counters in a synchronous process.

 

[Aquaa Marine]

like I said - your 2nd process is asynchronous - and you cannot use counters in asynchronous processes. You need to put the counters in a synchronous process.

Hello..
Well the coding is done in verilog.. Right?

 

[TrickyDicky]

Hello..
Well the coding is done in verilog.. Right?

No, its VHDL

 

[Aquaa Marine]

Thank you so much.