#### Ferfil

##### Newbie level 4

**Traffic Lights using moore state machine, Altera Quartus II, Verilog HDL**

**Please help me make a testbench for this code...**

module traffiic(clk, clear, R1, R2, R3, R4, X1,X2,X3,X4);

output [1:0] R1, R2, R3, R4;

reg [1:0] R1, R2, R3, R4;

input X1, X2, X3, X4;

input clk, clear;

reg [2:0] state;

reg [2:0] next_state;

parameter RED = 2'd0;

parameter YELLOW = 2'd1;

parameter GREEN = 2'd2;

parameter G2YDELAY = 10;

parameter Y2RDELAY = 3;

parameter s0 = 3'd0;

parameter s1 = 3'd1;

parameter s2 = 3'd2;

parameter s3 = 3'd3;

parameter s4 = 3'd4;

parameter s5 = 3'd5;

parameter s6 = 3'd6;

parameter s7 = 3'd7;

initial

begin

state <= s0;

next_state <= s0;

R1 <= GREEN;

R2 <= RED;

R3 <= RED;

R4 <= RED;

end

always @(posedge clk)

state <= next_state;

always @(state)

begin

case(state)

s0:

begin

R1 <= GREEN;

R2 <= RED;

R3 <= RED;

R4 <= RED;

end

s1:

begin

R1 <= YELLOW;

R2 <= RED;

R3 <= RED;

R4 <= RED;

end

s2:

begin

R1 <= RED;

R2 <= GREEN;

R3 <= RED;

R4 <= RED;

end

s3:

begin

R1 <= RED;

R2 <= YELLOW;

R3 <= RED;

R4 <= RED;

end

s4:

begin

R1 <= RED;

R2 <= RED;

R3 <= GREEN;

R4 <= RED;

end

s5:

begin

R1 <= RED;

R2 <= RED;

R3 <= YELLOW;

R4 <= RED;

end

s6:

begin

R1 <= RED;

R2 <= RED;

R3 <= RED;

R4 <= GREEN;

end

s7:

begin

R1 <= RED;

R2 <= RED;

R3 <= RED;

R4 <= YELLOW;

end

endcase

end

always @(state or clear or X1 or X2 or X3 or X4 )

begin

if (clear)

next_state <= s0;

else

begin

case(state)

s0:

begin

repeat (G2YDELAY) @(posedge clk);

next_state <= s1;

end

s1:

if(~X2)

begin

repeat (Y2RDELAY) @(posedge clk);

next_state <= s4;

end

else

begin

repeat (Y2RDELAY) @(posedge clk);

next_state <= s2;

end

s2:

begin

repeat (G2YDELAY) @(posedge clk);

next_state <= s3;

end

s3:

if(~X3)

begin

repeat (Y2RDELAY) @(posedge clk);

next_state <= s6;

end

else

begin

repeat (Y2RDELAY) @(posedge clk);

next_state <= s4;

end

s4:

begin

repeat (Y2RDELAY) @(posedge clk);

next_state <= s5;

end

s5:

if(~X4)

begin

repeat (Y2RDELAY) @(posedge clk);

next_state <= s0;

end

else

begin

repeat (Y2RDELAY) @(posedge clk);

next_state <= s6;

end

s6:

begin

repeat (Y2RDELAY) @(posedge clk);

next_state <= s7;

end

s7:

if(~X1)

begin

repeat (Y2RDELAY) @(posedge clk);

next_state <= s2;

end

else

begin

repeat (Y2RDELAY) @(posedge clk);

next_state <= s0;

end

default : next_state <= s0;

endcase

end

end

endmodule