Track length of clk signal in high-speed designing

[AK2009]

length of a signal

Hi,

I am new to high-speed designing and need help.

All the address lines , data lines need to be matched in length with the trace carrying clk signal. But how the optimum length of clk trace is decided?. Please help.

Regards

ak

 

[dipnirvana]

track length

This will depend on the slew rate of the clock. The distance should be equivalent to the time taken by one forth of the slew rate .

 

[DavidReina]

high speed data lines length tolerance

Hi,

There is a rule of thumb that says clock signals should be routed as short as possible, that is partially true, as dipnirvana said, it depends on the slew rate and frequency.

The best way to go is to perform a line length sweep analysis in spice... you will need to generate different models (Transmission Line, Via Model, etc) and get the IBIS model of the buffer being used, also the pkg model.

The main characteristics that you must take care in a clock signal are the slew rate, crossing point, overshoot and undershoot. Length affects the slew rate and the overshoot/undershoot. The slew rate has a decrease on the even multiples of quarter wavelength, and you should avoid this bumps... I really don't know the relationship between length and OS/US but I know there is one...


hope this helps

-D

 

[n_raghavan07]

fr4 speed rule of thumb

Hi,
The speed at which the electrical energy can travel along the route it known as the propagation velocity, where
VP = speed of light / √dielectric constant

Below is the basic rule(Distance =time x velocity)

Using
Time = 1/3 * rise time
εR = 4 (approximation for FR4)
C = 11.811 in/nSec (speed of light, in inches per nanosecond)
To find the length of route above which the integrity of the signal could become a problem:
LR = Time * VP
= Time * C / √ εR
LR = .33 * 11.811 / 2
= 1.95 in

Regards,
N.Raghavan

 

[FvM]

There is a rule of thumb that says clock signals should be routed as short as possible

Obviously, the said rule is only applicable for medium speed circuits. At higher speeds or when designing large PCBs, you should think about impedance matching instead. For a point-to-point connection, a simple source-sided series termination can achieve good signal quality in most cases.

 

[chakravarthy80pcb]

As for high speed designs we have to Refer the Manufacturer Datasheet of that component.

There they will mention clearly the space b/w Byte to byte and inner pairs spacing of ADDRESS and DATA Lines and also max clk length.

If N/A its difficult to mention the clk length correctly.

At that time we have to follow thumb rule for clk and maintain the same length for add and data lines within the tolerance of+/- 100 to +/-500mils.

hope this will help you.

cheers
chakri