Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

track and hold circuit for 8-bit folding adc

Status
Not open for further replies.

kickbeer

Full Member level 3
Joined
Nov 7, 2008
Messages
162
Helped
1
Reputation
2
Reaction score
0
Trophy points
1,296
Activity points
2,356
track and hold circuit

Hello,

Is there any recommedation whick track and hold i should use for my adc?

Input of that track and hold must be sinusoidal and has double ended output
 

Monady

Advanced Member level 4
Joined
Dec 1, 2008
Messages
111
Helped
12
Reputation
24
Reaction score
3
Trophy points
1,298
Activity points
2,165
folding adc

it depends to frequency.nevertheless i think you can use of simple switch with a capacitor (in the high speed ADCs). with fully differential topology, clock feedthrough will be removed. i think you can reach to the 48dB SNR, with this topology even in high frequency. as you know in high speed ADCs, you can't use of closed loop SH.
 

    kickbeer

    Points: 2
    Helpful Answer Positive Rating

kickbeer

Full Member level 3
Joined
Nov 7, 2008
Messages
162
Helped
1
Reputation
2
Reaction score
0
Trophy points
1,296
Activity points
2,356
track and hold

speed of my a/d converter would be around 70 MHz. Can your show me some example? link etc...
 

Monady

Advanced Member level 4
Joined
Dec 1, 2008
Messages
111
Helped
12
Reputation
24
Reaction score
3
Trophy points
1,298
Activity points
2,165
adc close-loop sample hold

your speed is not high, i used of mentioned SH in my project(8bit,1GSPS). besides one of the important factors for choose topology of SH is a type of your ADC. unfortunately i didn't design folded ADC yet. for example if output of SH must drive large cap(parasitic cap), you won't able to use of simple SH and you have to use of SH that contains opamp. in closed loop SH(with opamp), current of opamp will charge parasitic cap whereas hold voltage on sampling capacitor, determines voltage of SH output.
 

    kickbeer

    Points: 2
    Helpful Answer Positive Rating

kickbeer

Full Member level 3
Joined
Nov 7, 2008
Messages
162
Helped
1
Reputation
2
Reaction score
0
Trophy points
1,296
Activity points
2,356
track and hold adc

Monady said:
your speed is not high, i used of mentioned SH in my project(8bit,1GSPS). besides one of the important factors for choose topology of SH is a type of your ADC. unfortunately i didn't design folded ADC yet. for example if output of SH must drive large cap(parasitic cap), you won't able to use of simple SH and you have to use of SH that contains opamp. in closed loop SH(with opamp), current of opamp will charge parasitic cap whereas hold voltage on sampling capacitor, determines voltage of SH output.


i don't dunderstand what u meant by this 'drive large capacitance'??
 

Monady

Advanced Member level 4
Joined
Dec 1, 2008
Messages
111
Helped
12
Reputation
24
Reaction score
3
Trophy points
1,298
Activity points
2,165
adc track&hold circuit

for example in flash ADC, 2^n comparator exists. these comparators have a large parasitic cap (it belongs to the parasitic cap of inputs of comparators), thus SH must drive large parasitic cap.
 

    kickbeer

    Points: 2
    Helpful Answer Positive Rating

kickbeer

Full Member level 3
Joined
Nov 7, 2008
Messages
162
Helped
1
Reputation
2
Reaction score
0
Trophy points
1,296
Activity points
2,356
track & hold circuit

Monady said:
for example in flash ADC, 2^n comparator exists. these comparators have a large parasitic cap (it belongs to the parasitic cap of inputs of comparators), thus SH must drive large parasitic cap.


the number of comparator in folding adc is much less than from flash. Mine has 40 comparators. does this considered to have large capacitances? is total input capacitances of 2pf large?

thx
 

Monady

Advanced Member level 4
Joined
Dec 1, 2008
Messages
111
Helped
12
Reputation
24
Reaction score
3
Trophy points
1,298
Activity points
2,165
ieindia.org

you should compare 2pF with value of sampling capacitor . i think it's better to test one open loop SH although it seems that you need to use of SH with opamp.besides search for some thesis or paper about folded, surely you'll find some beneficial info about this issue.
Good luck
 

    kickbeer

    Points: 2
    Helpful Answer Positive Rating

Petre Petrov

Member level 3
Joined
Aug 5, 2009
Messages
58
Helped
7
Reputation
14
Reaction score
2
Trophy points
1,288
Location
Sofia
Activity points
1,780
track and hold circuit example

Hello!
At 70 MHz you should respect a lot of design rules and you should be almost professional to achieve guaranteed results.
But if you have a 100 times lower frequency it will be much easier.
Everything depends on your experience and resources.
May you will find something useful below:
Sample and hold basics:
https://www.iop.org/EJ/article/1674...quest-id=f8921ed2-1747-4166-9cec-8ab31b7ebdd3
https://specteclogistics.com/docs/70605/70605.pdf
https://analog.postech.ac.kr/3.Class/1.Classes/07_695O/SH.pdf
https://www.national.com/mpf/LF/LF398.html
https://www.national.com/an/AN/AN-294.pdf
https://www.intersil.com/data/fn/fn2858.pdf
https://www.analog.com/en/verifiedcircuits/CN0058/vc.html
ADCs:
https://www.national.com/pf/DC/ADC12L066.html
https://www.national.com/pf/DC/ADC08B3000.html
Sampling and conversion:
https://www.national.com/an/AN/AN-236.pdf
https://www.national.com/an/AN/AN-237.pdf
https://www.ieindia.org/pdf/88/88ET104.pdf
https://www.ieindia.org/pdf/89/89CP109.pdf
Hope that will help you a bit.
BR
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top