[SOLVED] top level of always block must be if statement!?

[terry8]

as title, when i synthesis with design compiler,

the tool told me that top level of always block must be if statement.

i really confuse why it just be case statement

the original verilog code

always @(posedge clk or negedge rst)
begin



    case(ps)  
    idle: 
      begin
      
       stop <= 0;
       d[10:0] <= 11'b100_0000_0000;
      end
    
   
    
    cal_cycle:
       begin
        case(q) //synopsys parallel_case
            
            
               0:;
               
               
               1:       begin
                          d<=11'b100_0000_0000;
                          i<=4'b1010;
                         
                        end
                        
                        
               2:        begin 
                          d<=11'b010_0000_0000;
                          i<=4'b1001;
                          
                         end
                         
                         
                         
               3,4:      begin 
                          d<=11'b001_0000_0000;
                          i<=4'b1000;
                        
                         end
                         
                         
                         
               5,6:     begin 
                          d<=11'b000_1000_0000;
                         i<=4'b0111;
                        
                         end
                         
                         
                         
               6,7:      begin 
                          d<=11'b000_0100_0000;
                         i<=4'b0110;
                          
                         end
                         
                         
                         
               default: begin 
                          d<=11'b000_0010_0000;
                          i<=4'b0101;
                          
                        end
          
         endcase   
           
           
       end //end cal_cycle
           

    search:
      case(i) //synopsys parallel_case
  
       4'b0000:
         begin
           if(!comp)   d[i]<=1'b0;
           else d[i] <=1'b1;
           stop <=1'b1;
   
         end
  
       default:
          begin
           if(!comp)   d[i]<=1'b0;
           else d[i] <=1'b1;
           d[i-1]<=1'b1;
           i<=i-1;
          end
          endcase
  
         
         

      
      
    finish:
       
         case ({up,dn}) //synopsys parallel_case

          //2'b10: d= d+1'b1;

          //2'b01: d= d-1'b1;

          2'b10: d[10:0] <= d[10:0]+1'b1;
                 
          2'b01: d[10:0] <= d[10:0]-1'b1;
          
          default:;
         endcase 
    
 endcase //ps
end //always

and i just add if statement then it work!but i dont know why?

always @(posedge clk or negedge rst)
begin
if (!rst) stop<=1'b0;

else 
    case(ps)  
    idle: 
      begin
      
       stop <= 0;
       d[10:0] <= 11'b100_0000_0000;
      end
    
   
    
    cal_cycle:
       begin
        case(q) //synopsys parallel_case
            
            
               0:;
               
               
               1:       begin
                          d<=11'b100_0000_0000;
                          i<=4'b1010;
                         
                        end
                        
                        
               2:        begin 
                          d<=11'b010_0000_0000;
                          i<=4'b1001;
                          
                         end
                         
                         
                         
               3,4:      begin 
                          d<=11'b001_0000_0000;
                          i<=4'b1000;
                        
                         end
                         
                         
                         
               5,6:     begin 
                          d<=11'b000_1000_0000;
                         i<=4'b0111;
                        
                         end
                         
                         
                         
               6,7:      begin 
                          d<=11'b000_0100_0000;
                         i<=4'b0110;
                          
                         end
                         
                         
                         
               default: begin 
                          d<=11'b000_0010_0000;
                          i<=4'b0101;
                          
                        end
          
         endcase   
           
           
       end //end cal_cycle
           

    search:
      case(i) //synopsys parallel_case
  
       4'b0000:
         begin
           if(!comp)   d[i]<=1'b0;
           else d[i] <=1'b1;
           stop <=1'b1;
   
         end
  
       default:
          begin
           if(!comp)   d[i]<=1'b0;
           else d[i] <=1'b1;
           d[i-1]<=1'b1;
           i<=i-1;
          end
          endcase
  
         
         

      
      
    finish:
       
         case ({up,dn}) //synopsys parallel_case

          //2'b10: d= d+1'b1;

          //2'b01: d= d-1'b1;

          2'b10: d[10:0] <= d[10:0]+1'b1;
                 
          2'b01: d[10:0] <= d[10:0]-1'b1;
          
          default:;
         endcase 
    
 endcase //ps
end //always

 

[permute]

you describe an async reset. in the first case, both clk and rst appear to be clocks -- there's nothing in the code that forces clk to be a clock, and rst to be a reset.

in the second case, there is a clear meaning of clk/rst.