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To use xilinx IP Core Generator need help!

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Matrix_YL

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Hi all


Can anyone tell me correct steps to use Core Generator in ISE !Actually I know how to generate IP core in Core Generator but I don't know which file shall be add in project when core generator generatre so many files (*.vhd and *.v I don't know how to use especially ).
Normally I just add *.xco to project and instantiate core it my module

Can you tell me my steps right or wrong ? or give me some advices or you common steps



Thanks in advance
 

echo47

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    Matrix_YL

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roza

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Add e.g. l2.xco to project
Open schematic
add element l2 to schematic menu add element below item All elemements

roza
 

freeinthewind

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if u call the IP, the .xco file is added to ur project automatically.
 

amit_8561

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to use IP core see its data sheet and in data sheet see the timin diagram related to ur application try to implement that using some logic
 

mann4uonlyed

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Have you seen this page in the ISE Help? It works for me in ISE 8.1i Project Navigator.
Working with CORE Generator IP [ISE Help]

I don't like Project Navigator. I usually build my projects from the command line using a makefile.

I have used vhdl fild to add but hoe to implement this project, as i am having error map-116?
 

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