To make netlist have the same reg names as those in verilog code

[jy0908]

I have some question about synthesis.
My question is that: Is there any way to keep the reg name during the synthesis?
I would like to give an example of my verilog source code.
In this code, I uses 4 regs: 'mem_read_data_r', 'mem_read_data_valid_r', 'mem_load_rd_r', and 'daddress_r'.

********************** verilog source ****************
module write_back
(
input i_clk,
input i_mem_stall,
input [31:0] i_mem_read_data,
input i_mem_read_data_valid,
input [9:0] i_mem_load_rd,
output [31:0] o_wb_read_data,
output o_wb_read_data_valid,
output [9:0] o_wb_load_rd,
input [31:0] i_daddress,
input i_daddress_valid
);

reg [31:0] mem_read_data_r;
reg mem_read_data_valid_r;
reg [9:0] mem_load_rd_r;
reg [31:0] daddress_r;

assign o_wb_read_data = mem_read_data_r;
assign o_wb_read_data_valid = mem_read_data_valid_r;
assign o_wb_load_rd = mem_load_rd_r;

always @( posedge i_clk )
if ( !i_mem_stall )
begin
mem_read_data_r <= i_mem_read_data;
mem_read_data_valid_r <= i_mem_read_data_valid;
mem_load_rd_r <= i_mem_load_rd;
daddress_r <= i_daddress;
end

endmodule
**********************************************************


After I synthesize verilog source code, I got this netlist.



******************************** Netlist *****************
DFF mem_read_data_valid_r_reg ( .D(n173), .CK(i_clk), .R(1'b0),.Q(o_wb_read_data_valid) );
...
DFF mem_load_rd_r_reg[0] ( .D(n171), .CK(i_clk), .R(1'b0), .Q(o_wb_load_rd[0]) );
...
DFF mem_read_data_r_reg[0] ( .D(n89), .CK(i_clk), .R(1'b0), .Q(o_wb_read_data[0]) );
***********************************************************

[Q1]
I would like to keep the reg names in the netlist the same as the verilog source.
Therefore, The output that I want to get looks like below:

******************************** What I want to get *****************
DFF mem_read_data_valid_r_reg ( .D(n173), .CK(i_clk), .R(1'b0), .Q(mem_read_data_valid_r) );
...
DFF mem_load_rd_r_reg[0] ( .D(n171), .CK(i_clk), .R(1'b0), .Q(mem_load_rd_r[0]) );
...
DFF mem_read_data_r_reg[0] ( .D(n89), .CK(i_clk), .R(1'b0), .Q(mem_read_data_r[0]) );
**********************************************************************

[Q2]
In the netlist, 'daddress_r' node is not shown. (Other 3 regs are synthesized with FFs)
I think the DFF related to the 'daddress_r' signal was optimized and not implemented with DFF during synthesis.
How can I have DFF for 'daddress_r' in my netlist?

In order to solve [Q1], [Q2] problem, I've tried 'set_dont_touch' but failed. Am I missing something?

Thanks in advance.

 

[RBB]

This has worked for me in the past, but I haven't tried it lately or with the latest version of Design Compiler. I'm assuming you're using Design Compiler. Try placing this in your RTL:

// synopsys dc_script_begin
// set_dont_touch mem_read_data_r
// set_dont_touch mem_read_data_valid_r
// set_dont_touch mem_load_rd_r
// set_dont_touch daddress_r
// synopsys dc_script_end

reg [31:0] mem_read_data_r;
reg mem_read_data_valid_r;
reg [9:0] mem_load_rd_r;
reg [31:0] daddress_r;

 

[jy0908]

Hi. RBB,
I got these Warnings and Errors when I put suggested "set_dont_touch" codes in my verilog source code.
I think it is because... as soon as DC reads the verilog source code (such as read_verilog), it changes reg name in advance to synthesize it.


*********************************
Warning: Can't find object 'mem_read_data_r' in design 'a25_write_back'. (UID-95)
Error: Value for list 'object_list' must have 1 elements. (CMD-036)
Warning: Can't find object 'mem_read_data_valid_r' in design 'a25_write_back'. (UID-95)
Error: Value for list 'object_list' must have 1 elements. (CMD-036)
Warning: Can't find object 'mem_load_rd_r' in design 'a25_write_back'. (UID-95)
Error: Value for list 'object_list' must have 1 elements. (CMD-036)
Warning: Can't find object 'daddress_r' in design 'a25_write_back'. (UID-95)
Error: Value for list 'object_list' must have 1 elements. (CMD-036)
*********************************


It's really difficult than I expected

 

[RBB]

Instead of using read_verilog try:

analyze -format verilog blah.v
elaborate blah -update

 

[jy0908]

Oh. I've already used both "read_verilog" and "analyzed-elaborate" for the synthesis.

But, it doesn't work.

Anyway, thank you very much.

By the way, why does the optimization occurs in verilog read step? (I've checked the reg names are changed after reading source file)

 

[RBB]

No idea. This has always worked for me in the past, so it's either a version issue or a configuration issue. I'd recommend searching on SolvNet.

 

[jy0908]

Hi. RBB, I really appreciate it

Could you let me know which version of DC you did you use?

 

[RBB]

Tried it with both 2008.09-SP1 & 2010.03-SP4 with no errors.

---------- Post added at 18:47 ---------- Previous post was at 18:14 ----------

I looked into it & it's because your internal signal names really don't do anything. They just get pseudo-buffered via the assign statements, so DC is just ripping them out. Also you daddress_r bus doesn't go anywhere so DC removes it completely.

 

[jy0908]

Hi. RBB,

Oh I see.

I really appreciate it

The code you gave me works well when I change my code as you suggested.

Thank you so much