jy0908
Newbie level 5
I have some question about synthesis.
My question is that: Is there any way to keep the reg name during the synthesis?
I would like to give an example of my verilog source code.![Smile :) :)](data:image/gif;base64,R0lGODlhAQABAIAAAAAAAP///yH5BAEAAAAALAAAAAABAAEAAAIBRAA7)
In this code, I uses 4 regs: 'mem_read_data_r', 'mem_read_data_valid_r', 'mem_load_rd_r', and 'daddress_r'.
********************** verilog source ****************
module write_back
(
input i_clk,
input i_mem_stall,
input [31:0] i_mem_read_data,
input i_mem_read_data_valid,
input [9:0] i_mem_load_rd,
output [31:0] o_wb_read_data,
output o_wb_read_data_valid,
output [9:0] o_wb_load_rd,
input [31:0] i_daddress,
input i_daddress_valid
);
reg [31:0] mem_read_data_r;
reg mem_read_data_valid_r;
reg [9:0] mem_load_rd_r;
reg [31:0] daddress_r;
assign o_wb_read_data = mem_read_data_r;
assign o_wb_read_data_valid = mem_read_data_valid_r;
assign o_wb_load_rd = mem_load_rd_r;
always @( posedge i_clk )
if ( !i_mem_stall )
begin
mem_read_data_r <= i_mem_read_data;
mem_read_data_valid_r <= i_mem_read_data_valid;
mem_load_rd_r <= i_mem_load_rd;
daddress_r <= i_daddress;
end
endmodule
**********************************************************
After I synthesize verilog source code, I got this netlist.
******************************** Netlist *****************
DFF mem_read_data_valid_r_reg ( .D(n173), .CK(i_clk), .R(1'b0),.Q(o_wb_read_data_valid) );
...
DFF mem_load_rd_r_reg[0] ( .D(n171), .CK(i_clk), .R(1'b0), .Q(o_wb_load_rd[0]) );
...
DFF mem_read_data_r_reg[0] ( .D(n89), .CK(i_clk), .R(1'b0), .Q(o_wb_read_data[0]) );
***********************************************************
[Q1]
I would like to keep the reg names in the netlist the same as the verilog source.
Therefore, The output that I want to get looks like below:
******************************** What I want to get *****************
DFF mem_read_data_valid_r_reg ( .D(n173), .CK(i_clk), .R(1'b0), .Q(mem_read_data_valid_r) );
...
DFF mem_load_rd_r_reg[0] ( .D(n171), .CK(i_clk), .R(1'b0), .Q(mem_load_rd_r[0]) );
...
DFF mem_read_data_r_reg[0] ( .D(n89), .CK(i_clk), .R(1'b0), .Q(mem_read_data_r[0]) );
**********************************************************************
[Q2]
In the netlist, 'daddress_r' node is not shown. (Other 3 regs are synthesized with FFs)
I think the DFF related to the 'daddress_r' signal was optimized and not implemented with DFF during synthesis.
How can I have DFF for 'daddress_r' in my netlist?
In order to solve [Q1], [Q2] problem, I've tried 'set_dont_touch' but failed. Am I missing something?
Thanks in advance.
My question is that: Is there any way to keep the reg name during the synthesis?
I would like to give an example of my verilog source code.
In this code, I uses 4 regs: 'mem_read_data_r', 'mem_read_data_valid_r', 'mem_load_rd_r', and 'daddress_r'.
********************** verilog source ****************
module write_back
(
input i_clk,
input i_mem_stall,
input [31:0] i_mem_read_data,
input i_mem_read_data_valid,
input [9:0] i_mem_load_rd,
output [31:0] o_wb_read_data,
output o_wb_read_data_valid,
output [9:0] o_wb_load_rd,
input [31:0] i_daddress,
input i_daddress_valid
);
reg [31:0] mem_read_data_r;
reg mem_read_data_valid_r;
reg [9:0] mem_load_rd_r;
reg [31:0] daddress_r;
assign o_wb_read_data = mem_read_data_r;
assign o_wb_read_data_valid = mem_read_data_valid_r;
assign o_wb_load_rd = mem_load_rd_r;
always @( posedge i_clk )
if ( !i_mem_stall )
begin
mem_read_data_r <= i_mem_read_data;
mem_read_data_valid_r <= i_mem_read_data_valid;
mem_load_rd_r <= i_mem_load_rd;
daddress_r <= i_daddress;
end
endmodule
**********************************************************
After I synthesize verilog source code, I got this netlist.
******************************** Netlist *****************
DFF mem_read_data_valid_r_reg ( .D(n173), .CK(i_clk), .R(1'b0),.Q(o_wb_read_data_valid) );
...
DFF mem_load_rd_r_reg[0] ( .D(n171), .CK(i_clk), .R(1'b0), .Q(o_wb_load_rd[0]) );
...
DFF mem_read_data_r_reg[0] ( .D(n89), .CK(i_clk), .R(1'b0), .Q(o_wb_read_data[0]) );
***********************************************************
[Q1]
I would like to keep the reg names in the netlist the same as the verilog source.
Therefore, The output that I want to get looks like below:
******************************** What I want to get *****************
DFF mem_read_data_valid_r_reg ( .D(n173), .CK(i_clk), .R(1'b0), .Q(mem_read_data_valid_r) );
...
DFF mem_load_rd_r_reg[0] ( .D(n171), .CK(i_clk), .R(1'b0), .Q(mem_load_rd_r[0]) );
...
DFF mem_read_data_r_reg[0] ( .D(n89), .CK(i_clk), .R(1'b0), .Q(mem_read_data_r[0]) );
**********************************************************************
[Q2]
In the netlist, 'daddress_r' node is not shown. (Other 3 regs are synthesized with FFs)
I think the DFF related to the 'daddress_r' signal was optimized and not implemented with DFF during synthesis.
How can I have DFF for 'daddress_r' in my netlist?
In order to solve [Q1], [Q2] problem, I've tried 'set_dont_touch' but failed. Am I missing something?
Thanks in advance.