to increase the speed of Design

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niraj_m

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Hi
Can we design a flop to work on both edges of clock ? In this scenario how do we takecare of timing and metastability issues ?

Pls brainstorm your points .

Also if you have any paper or link pls do point. It really helps me .

Thanks in advance
 

You cannot have a flop working on both edges of the clock, that why it is called an edge triggered device. You have to decide which edge of the clock you want to use.
 



Parallelization increases the speed of your circuit. Use dual/quad pumping for clocking.
 

Thanks for your reply.

Yes true that flop needs to latch on edge of clock , so do current philosophy of flop. Also we can construct a dual edge flop , wherein flop latches data on both edges on clock ,yes it tedious process .
I have got few info on these , further links helps .
 

iwpia50s said:
You cannot have a flop working on both edges of the clock, that why it is called an edge triggered device. You have to decide which edge of the clock you want to use.
Click to expand...

You can always design a dual edge triggered flip flop but you do not normally find them in your designs. Why? because very few EDA tools support them.
 


Dual-edge flops typically used to reduce power consumption in design. Most of modern synthesis and backend tools work properly with such flops.
 

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