Iam working on memory design which requries a clock. i need to detect the Rising edge and Falling edge of the clock and to generate a corresponding pulse for for falling and rising edge. using cmos logic or nmos logic
Why dont you use a complementary clocking scheme with D-Flops as the data capture devices. The logic can be realized using a X-OR gate to generate a pulse.
If the synchronization is not important, you can take the clock signal and then pass it through some delay and take both of them to an X-OR gate. This will give pulses at both the rising and falling edges of the clock signal.
Be careful about the component selection. I suppose that you are working on DDR circuits