worker8
Newbie level 1
Hi,
I've written a system in VHDL and tested the behavioral simulation in ModelSim. The system performs as intended in ModelSim, however, when I compiled it in Quartus II, everything passes except the Timing Requirements.
I'm using Altera DE2 Board.
Thanks in advance!
I've written a system in VHDL and tested the behavioral simulation in ModelSim. The system performs as intended in ModelSim, however, when I compiled it in Quartus II, everything passes except the Timing Requirements.
- I would like to ask what could have possibly cause the Timing Requirements to fail?
- Are there any good practices in writing VHDL that can prevent the Timing Requirements to fail?
- How to debug a Timing Requirement problem ?
I'm using Altera DE2 Board.
Thanks in advance!