Timing Requirements Problem in Quartus II

[worker8]

Hi,

I've written a system in VHDL and tested the behavioral simulation in ModelSim. The system performs as intended in ModelSim, however, when I compiled it in Quartus II, everything passes except the Timing Requirements.

• I would like to ask what could have possibly cause the Timing Requirements to fail?
• Are there any good practices in writing VHDL that can prevent the Timing Requirements to fail?
• How to debug a Timing Requirement problem ?

I'm using Altera DE2 Board.

Thanks in advance!

 

[amitjagtap]

hey,
Timing problems are sometimes logic dependent..... You can write a same code in different manner.
Well If you want to understand the timing failures reason you have to have knowledge of FF timings and FPGA architectures and some practice to write HDL code.
Also, when you compile any code in modelsim it dosent consider particular FPGA architecture, whereas in tool like Quartus it is compiled for that particular FPGA.

 

[TrickyDicky]

In most cases, timing problems are caused by having too much logic between registers, or simply not making your design fully synchronous in the first place.

A design that has failed timing does not garantee there is a problem, it just suggests you may (or probably will) see odd things happen when you run the actual chip.

If your problem is register to register timing problems, then you either need to lower your clock speed or re-pipeline your design (ie. modify the VHDL)
If you problem is caused by lack of a synchronous design, the easiest fix is to make it synchronous.