timing of pipelined adc

[lhlbluesky]

i want to ask a simple question,for a pipelined adc,the odd and even stages work in non-overlapped clock phase phi1 and phi2,if the odd stages(for example,the first stage)work in phi1 phase,then the even stages(for example,the second stage)work in phi2 phase,but what phase do the sub-adc(comp) and sub-dac of the odd and even stages work?i think sub-adc(comp) and sub-dac of odd stages work in phi1 and phi2;and sub-adc(comp) and sub-dac of even stages work in phi2 and phi1;is that right?
if so,i have another question,when i simulate the first and second stage using vdc source separately,they work well;but when connect them together,the second stage
can't work well,the output of sub-adc is always 01 in the full range(10 bit 1.5 bit per stage);when i simulate the sub-adc with vdc source,it works well,too;confused.
the first stage works well ,i think this is because i use vdc source in the first stage,but the input of the second stage is the output of the first stage,and it has a process of settling;but when does the sub-adc(comp)work for the second stage?
really need help,thanks all for reply.
thanks.

 

[jeffsky520]

hi I think maybe its your timing wrong, so
make sure of your circuit connection right first.

 

[lhlbluesky]

i'm sure that the connect is no problem;and i think it's the problem of timing,too;but what's the problem?
the clock of the comp(sub-adc) is phi1(sample phase) or phi2(hold phase),or some else improved clock?

 

[A.Anand Srinivasan]

the first stage second stage thing you are talking about is confusing me.... i'll explain in the way i know hope it helps...

the sub adc(comparator) uses a clock which is a little earlier known as early phase clock.... i have worked on pipelined adc and i needed 4 clocks.... the early phase clock is needed because the comparator output has to be ready early so that the appropriate value that to be subtracted in order to generate the residue is chosen before input reaches opamp...

about the second stage not working.... i think it is due to capacitance... when simulating separately the capacitance of input or output is not taken into account.... this would have caused loading....