The basic questions will be on
1. Clock constraints (master clock, generated clock, clock skew, jitter, clock network delay, source delay)
2. Input and output constraints
3. Virtual clock and the use of it
4. False path and multi cycle path. How will you identify them.
5. How will you fix setup and hold violations
6. What is PVT corner and its effect on synthesis and timing analysis
7. What is OCV analysis
8. Effect of wireload model on timing analysis
9. What is DRC violation. How will you fix.
10. Timing checks on clock gating cells
11. Reset recovery time and removal time
12. Scan insertion
13. Clock gating cells insertion
14. Area and Power
15. Content of technology library
16. why do we need link library
etc.