Timing during Synthesis process

[limitless_21]

HI all,

Can anyone let me know timing related questions which can be asked during synthesis process ? or any other timing concepts or timing related questions which can be asked during interview.

Thanks
Limitless_21

 

[mr_vasanth]

The basic questions will be on
1. Clock constraints (master clock, generated clock, clock skew, jitter, clock network delay, source delay)
2. Input and output constraints
3. Virtual clock and the use of it
4. False path and multi cycle path. How will you identify them.
5. How will you fix setup and hold violations
6. What is PVT corner and its effect on synthesis and timing analysis
7. What is OCV analysis
8. Effect of wireload model on timing analysis
9. What is DRC violation. How will you fix.
10. Timing checks on clock gating cells
11. Reset recovery time and removal time
12. Scan insertion
13. Clock gating cells insertion
14. Area and Power
15. Content of technology library
16. why do we need link library
etc.

 

[limitless_21]

Hey thanks for providing the list of questions which can be asked.
But just wanted to know a few things more on the above few questions.

> Like regarding clock gating cells insertion and the timing checks which needs to applied on them during synthesis ?

> What is the procedure by which the tool ensures that the clock gating cells have to be inserted within the RTL code?
> Where are clock gating cells present ?
> Is the clock gating logic written out in the RTL code itself ?
> What is OCV ?

Thanks
limitless_21

The basic questions will be on
1. Clock constraints (master clock, generated clock, clock skew, jitter, clock network delay, source delay)
2. Input and output constraints
3. Virtual clock and the use of it
4. False path and multi cycle path. How will you identify them.
5. How will you fix setup and hold violations
6. What is PVT corner and its effect on synthesis and timing analysis
7. What is OCV analysis
8. Effect of wireload model on timing analysis
9. What is DRC violation. How will you fix.
10. Timing checks on clock gating cells
11. Reset recovery time and removal time
12. Scan insertion
13. Clock gating cells insertion
14. Area and Power
15. Content of technology library
16. why do we need link library
etc.

 

[ro9ty]

There are several ways to implement clock gating. The key concept is that the enable signal that goes to all the flops will be used to AND/OR with the clock signal (usually with a latch to prevent glitches).
Nowadays, most of the Integrated clock gating (ICG) is done by the RTL designer. He will simply have to instantiate the clock gating cell which is included as a cell in the library and during synthesis the tool will automatically pick it up.
Another way is to include it as enable conditions in the RTL so that the synthesis tool can easily fathom it is a clock-gating logic.
Another, lesser used method is to use special tool (low-power) which are modelled to insert clock-gates in specific zones with very high switching activity and deprived of clock-gating logic.